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EM77930
USB + BB Controller
Product Specification
DOC. VERSION 1.0
ELAN MICROELECTRONICS CORP.
August 2007
Trademark Acknowledgments: IBM is a registered trademark and PS/2 is a trademark of IBM. Windows is a trademark of Microsoft Corporation. ELAN and ELAN logo are trademarks of ELAN Microelectronics Corporation.
Copyright (c) 2007 by ELAN Microelectronics Corporation
All Rights Reserved
Printed in Taiwan
The contents of this specification are subject to change without further notice. ELAN Microelectronics assumes no responsibility concerning the accuracy, adequacy, or completeness of this specification. ELAN Microelectronics makes no commitment to update, or to keep current the information and material contained in this specification. Such information and material may change to conform to each confirmed order. In no event shall ELAN Microelectronics be made responsible for any claims attributed to errors, omissions, or other inaccuracies in the information or material contained in this specification. ELAN Microelectronics shall not be liable for direct, indirect, special incidental, or consequential damages arising from the use of such information or material. The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and may be used or copied only in accordance with the terms of such agreement. ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of ELAN Microelectronics product in such applications is not supported and is prohibited. NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY ANY MEANS WITHOUT THE EXPRESSED WRITTEN PERMISSION OF ELAN MICROELECTRONICS.
ELAN MICROELECTRONICS CORPORATION
Headquarters: No. 12, Innovation Road 1 Hsinchu Science Park Hsinchu, Taiwan 30077 Tel: +886 3 563-9977 Fax: +886 3 563-9966 http://www.emc.com.tw Hong Kong: Elan (HK) Microelectronics Corporation, Ltd. Flat A, 19F., World Tech Centre 95 How Ming Street, Kwun Tong Kowloon, HONG KONG Tel: +852 2723-3376 Fax: +852 2723-7780 elanhk@emc.com.hk Shenzhen: Elan Microelectronics Shenzhen, Ltd. 3F, SSMEC Bldg., Gaoxin S. Ave. I Shenzhen Hi-tech Industrial Park (South Area), Shenzhen CHINA 518057 Tel: +86 755 2601-0565 Fax: +86 755 2601-0500 USA: Elan Information Technology Group (USA) 1821 Saratoga Ave., Suite 250 Saratoga, CA 95070 USA Tel: +1 408 366-8225 Fax: +1 408 366-8220
Shanghai: Elan Microelectronics Shanghai, Ltd. #23, Zone 115, Lane 572, Bibo Rd. Zhangjiang Hi-Tech Park Shanghai, CHINA 201203 Tel: +86 21 5080-3866 Fax: +86 21 5080-4600
Contents
Contents
1 2 General Description.....................................................................................................1 Features ........................................................................................................................1 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 3 4 5 6 Core...................................................................................................................... 1 Oscillators/System Clocks ................................................................................... 2 Input and Output (I/O) Pins.................................................................................. 2 Timers and Counters ........................................................................................... 2 Interrupt Sources and Features........................................................................... 2 Baseband ............................................................................................................. 3 Universal Serial Bus (USB) ................................................................................. 4 Pulse Width Modulation (PWM)........................................................................... 4
2.9 Built-in Voltage Regulator .................................................................................... 4 Pin Assignment ............................................................................................................5 Pin Description.............................................................................................................6 Block Diagram..............................................................................................................7 Memory .........................................................................................................................8 6.1 Program Memory ................................................................................................. 8 6.2 RAM-Register...................................................................................................... 9 Function Description.................................................................................................29 7.1 Special Purpose Registers ................................................................................ 29
7.1.1 7.1.2 7.1.3 7.1.4 7.1.5 7.1.6 7.1.7 7.1.8 7.1.9 7.1.10 7.1.11 7.1.12 7.1.13 7.1.14 7.1.15 7.1.16 7.1.17 7.1.18 7.1.19 7.1.20 Accumulator - ACC .......................................................................................... 29 Indirect Addressing Contents - IAC0 and IAC1 ............................................... 29 Program Counter HPC and LPC ...................................................................... 29 Status Register -SR ......................................................................................... 29 RAM Bank Selector - RAMBS0 and RAMBS1 ................................................ 30 ROM Page Selector - ROMPS ........................................................................ 30 Indirect Addressing Pointers - IAP0 and IAP1 ................................................. 30 Indirect Address Pointer Direction Control Register - IAPDR.......................... 31 Table Look-up Pointers - LTBL and HTBL ...................................................... 31 Stack Pointer - STKPTR .................................................................................. 31 Repeat Counter - RPTC .................................................................................. 31 Real Time Clock Counter - RTCC.................................................................... 31 Interrupt Flag Register - INTF.......................................................................... 31 Key Wake-up Flag Register - KWUAIF and KWUBIF ..................................... 32 I/O Port Registers - PTA ~ PTF........................................................................ 32 16-bit Free Run Counter (FRC) - LFRC, HFRC and LFRCB .......................... 32 PWM Duty - DT0L/DT0H ................................................................................. 32 PWM Period - PRD0L/PRD0H......................................................................... 32 PWM Duty Latch - DL0L/DL0H........................................................................ 32 BB Address Register - RFAAR ........................................................................ 32
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Product Specification (V1.0) 08.20.2007
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Contents
7.1.21 BB Data Buffer Register - RFDB ..................................................................... 32 7.1.22 BB Data Read/Write Control Register - RFACR .............................................. 33 7.1.23 BB Interrupt Flag Register - RFINTF ............................................................... 33
7.2 7.3
Dual Port Register.............................................................................................. 33 System Status, Control and Configuration Registers........................................ 33
7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.3.6 7.3.7 7.3.8 7.3.9 7.3.10 7.3.11 7.3.12 Peripherals Enable Control - PRIE .................................................................. 33 Interrupts Enable Control - INTE ..................................................................... 34 Key Wake-up Enable Control - KWUAIE and KWUBIE................................... 34 External Interrupts Edge Control - EINTED..................................................... 35 I/O Control Registers - IOCA~IOCF ................................................................ 35 Pull-up Resistance Control Registers for Ports - PUCA~PUCF ...................... 35 Open Drain Control Registers of Port B - ODCB............................................. 35 Timer Clock Counter Controller - TCCC .......................................................... 36 Free Run Counter Controller - FRCC .............................................................. 36 Watchdog Timer Controller - WDTC ................................................................ 37 PWM Control Register - PWMCR.................................................................... 38 BB Interrupt Control Register - RFINTE .......................................................... 38
7.4 8
USB Status, Control and Configuration Registers ............................................ 38
7.5 Code Option (ROM-0x2FFF) ............................................................................. 38 Base Band (BB)..........................................................................................................39 8.1 BB: Standard Interface to the RFW102 Series.................................................. 39
8.1.1 8.1.2 8.1.3 8.1.4 Features............................................................................................................ 39 Description........................................................................................................ 40 I/O and Package Description............................................................................ 41 BB Architecture ................................................................................................. 42 Reset ................................................................................................................ 43 Power Saving Modes........................................................................................ 43 8.2.2.1 Power-Down Mode ............................................................................ 43 8.2.2.2 Idle Mode ........................................................................................... 43 Preamble Correlation........................................................................................ 44 Refresh Bit ........................................................................................................ 44 Bit Structure ...................................................................................................... 45 CRC .................................................................................................................. 46 RX FIFO............................................................................................................ 46 TX FIFO ............................................................................................................ 47 Interrupt Driver.................................................................................................. 48 Packet Size....................................................................................................... 49 NET_ID and NODE_ID Filters .......................................................................... 49 Carrier-Sense ................................................................................................... 50 8.2.12.1 RFWaves Carrier-Sense Algorithm ................................................... 50 Receiver Reference Capacitor Discharge ........................................................ 52 Changing the BB Configuration ........................................................................ 52 Input Synchronizer............................................................................................ 52
Product Specification (V1.0) 08.20.2007
8.2
BB Description ................................................................................................... 43
8.2.1 8.2.2
8.2.3 8.2.4 8.2.5 8.2.6 8.2.7 8.2.8 8.2.9 8.2.10 8.2.11 8.2.12 8.2.13 8.2.14 8.2.15
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Contents
8.3
Register Description........................................................................................... 53
8.3.1 8.3.2 8.3.3 8.3.4 8.3.5 8.3.6 8.3.7 8.3.8 8.3.9 8.3.10 8.3.11 8.3.12 8.3.13 8.3.14 8.3.15 8.3.16 Bit Length Register (BLR)................................................................................. 53 Preamble Low Register (PRE-L) ...................................................................... 53 Preamble High Register (PRE-H)..................................................................... 53 Packet Parameter Register (PPR).................................................................... 53 System Control Register 1 (SCR1)................................................................... 55 System Control Register 2 (SCR2)................................................................... 55 System Control Register 3 (SCR3)................................................................... 56 System Control Register 4 (SCR4)................................................................... 58 Transmit FIFO Status Register (TFSR) ............................................................ 58 Receive FIFO Status Register (RFSR)............................................................. 58 Location Control Register (LCR) ...................................................................... 59 Node Identity Register (BIR)............................................................................. 60 Net Identity Register (NIR) ............................................................................... 60 System Status Register (SSR) ......................................................................... 60 Packet Size Register (PSR) ............................................................................. 62 Carrier Sense Register (CSR) .......................................................................... 62 Interrupt Enable Register (IER) ........................................................................ 63 Interrupt Identification Register (IIR)................................................................. 64
8.4
Interrupt Registers ............................................................................................. 63
8.4.1 8.4.2
8.5 8.6
List of BB Register Mapping .............................................................................. 65 MCU BB Control Registers ................................................................................ 66
8.6.1 8.6.2 Control Registers List ....................................................................................... 66 BB Control Example ......................................................................................... 67
9
Universal Serial Bus (USB).......................................................................................69 9.1 9.2 9.3 9.4 9.5 Block Diagram.................................................................................................... 69 USB FIFO Allocation .......................................................................................... 69 Pin Description ................................................................................................... 70 Timing Diagram of MCU Interface ..................................................................... 71 USB Device Register Summary ........................................................................ 72
9.5.1 9.5.2 9.5.3 9.5.4 9.5.5 9.5.6 9.5.7 9.5.8 9.5.9 9.5.10 9.5.11 9.5.12 9.5.13 General Control Register (GCNTR).................................................................. 73 Endpoint n Control Register (EP1/2/3CNTR) ................................................... 74 Endpoint Interrupt Event Register (EPINTR).................................................... 74 Endpoint Interrupt Event Enable Register (EPINTE)........................................ 76 State Interrupt Event Register (STAINTR)........................................................ 76 State Interrupt Event Enable Register (STAINTE)............................................ 76 Function Address Register (FAR) ..................................................................... 77 Endpoint 0 RX Token Register (EP0RXTR) ..................................................... 77 Endpoint 0 RX Command/Status Register (EP0RXCSR) ................................ 77 Endpoint 0 TX Command/Status Register (EP0TXCSR) ................................. 78 Endpoint 0 RX Count Register (EP0RXCTR)................................................... 79 Endpoint0 TX Count Register (EP0TXCTR)..................................................... 79 Endpoint 0 RX Data Register (EP0RXDAR)..................................................... 80
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Contents
9.5.14 9.5.15 9.5.16 9.5.17 9.5.18 9.5.19 9.5.20 9.5.21
Endpoint 0 TX Data Register (EP0TXDAR) ..................................................... 80 Endpoint n Command/Status Register (EPnCSR) ........................................... 80 Endpoint n Count Register (EPnCTR).............................................................. 82 Endpoint n Data Register (EPnDAR)................................................................ 82 USB Device SOF Event Register (HINTR)....................................................... 82 USB Device SOF Event Enable Register (HINTE)........................................... 82 Frame Number Low-Byte Register (FNLR) ...................................................... 82 Frame Number High-Byte Register (FNHR)..................................................... 82
10
Pulse Width Modulation (PWM)................................................................................83 10.1 Overview ............................................................................................................ 83 10.2 PWM Control Registers ..................................................................................... 84 10.3 PWM Programming Procedures/Steps.............................................................. 85 Interrupts.....................................................................................................................86 11.1 Introduction ........................................................................................................ 86 Circuitry of Input and Output Pins...........................................................................88 12.1 Introduction ........................................................................................................ 88 Timer/Counter System ..............................................................................................88 13.1 Introduction ........................................................................................................ 88 13.2 Time Clock Counter (TCC) ................................................................................ 88
13.2.1 Block Diagram of TCC ...................................................................................... 89 13.2.2 TCC Control Registers ..................................................................................... 89 13.2.3 TCC Programming Procedures/Steps .............................................................. 90
11 12 13
13.3 Free Run Counter .............................................................................................. 90
13.3.1 Block Diagram of FRC...................................................................................... 90 13.3.2 FRC Control Registers ..................................................................................... 91 13.3.3 FRC Programming Procedures/Steps .............................................................. 91
14
Reset and Wake Up....................................................................................................92 14.1 Reset .................................................................................................................. 92 14.2 The Status of RST, T, and P of STATUS Register ............................................. 92 14.3 System Set-up (SSU) Time................................................................................ 92 14.4 Wake-up Procedure on Power-on Reset........................................................... 93 Oscillators...................................................................................................................94 15.1 Introduction ........................................................................................................ 94 15.2 Clock Signal Distribution.................................................................................... 94 15.3 PLL Oscillator..................................................................................................... 94 Low-Power Mode .......................................................................................................95 16.1 Introduction ........................................................................................................ 95 16.2 Green Mode ....................................................................................................... 95 16.3 Sleep Mode ........................................................................................................ 96
15
16
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Contents
17 18
Instruction Description .............................................................................................96 16.1 Instruction Set Summary ................................................................................... 96 Electrical Specification .............................................................................................99 18.1 Absolute Maximum Ratings ............................................................................... 99 18.2 DC Electrical Characteristic ............................................................................... 99 18.3 Voltage Detector Electrical Characteristic ....................................................... 100 18.4 AC Electrical Characteristic ............................................................................. 100
18.4.1 MCU................................................................................................................ 100 18.4.2 BB ................................................................................................................... 101
19 20
Application Circuit ...................................................................................................102 Pad Description........................................................................................................103
APPENDIX
A B Package Type ...........................................................................................................105 Package Information ...............................................................................................105
Product Specification (V1.0) 08.20.2007
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Contents
Specification Revision History
Doc. Version 1.0 Revision Description Initial released version Date 2007/08/20
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Product Specification (V1.0) 08.20.2007
EM77930
USB+BB Controller
1
General Description
The EM77930 from ELAN Technology is a low-cost and high performance 8-bit CMOS advance RISC architecture microcontroller device. It has an on-chip 1-Mbps RF driver Baseband (BB), Universal Serial Bus (USB), one Pulse Width Modulation (PWM) with 16-bit resolution, an 8-bit Timer Clock Counter (TCC) and a 16-bit Free Run Timer, Key Wake-up function (KWU), Power-on Reset (POR), Watchdog Timer (WDT), and power saving Sleep Mode. All these features combine to ensure applications require the least external components, hence, not only reduce system cost, but also have the advantage of low power consumption and enhanced device reliability. The 44-pin EM77930 is available in a very cost-effective ROM version. It is also suitable for wireless base-band and USB device production.
2
Features
2.1 Core
Operating Voltage Range: 2.2V ~ 3.6V DC Operating Temperature Range: 0C ~ 70C Operating Frequency Range: DC ~ 48MHz (1 clock/cycle) 6MHz external clock source 6/12/24/48 MHz Core & BB clock 6/48MHz internal USB clock (Low/Full speed) 12K x 16 bits of on-chip Program ROM 1216 x 8 bits of on-chip Register (SRAM) plus USB indirect addressing RAM Watchdog Timer (WDT) 16-level stacks for both CALL and interrupt subroutine Internal Power-on Reset (POR) function. All single cycle (1 clock) instruction except for conditional branches which are two or three cycles Direct, indirect and relative addressing modes Low power, high speed CMOS technology Power consumption: < 4 mA @ 3.3V, 6 MHz < 1 A standby current
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
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EM77930
USB+BB Controller
2.2 Oscillators/System Clocks
Three oscillator options:
Crystal/Resonate oscillator of high frequency PLL oscillator: 6MHz, 12 MHz, 24 MHz, and 48 MHz (External crystal should be 6 MHz) Internal RC oscillator (32kHz)
Three modes of system clocks:
Sleep mode Green mode Normal mode
Internal RC oscillator for Power-on Reset (POR) and Watchdog Timer (WDT)
2.3 Input and Output (I/O) Pins
Max. of 30 I/O pins Pull-up resistor options Key Wake-up function Open drain output options
2.4 Timers and Counters
Programmable 8-bit real Time Clock/Counter (TCC) with prescaler and overflow interrupt 16-bit Free Run Counter (FRC) with overflow interrupt
2.5 Interrupt Sources and Features
Hardware priority check Different interrupt vectors Interrupts:
Key Wake up External pin interrupt 16-bit Free Run Counter Overflow TCC (time-base) overflow One complete period of Pulse Width Modulation (PWM) Base band (BB) function interrupts CSD: carrier sense detection

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Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
EM77930
USB+BB Controller
TX_AE: TX_FIFO almost full RX_AF: RX_FIFO almost full TX_ EMPTY: finish a transmitting a package RX_OF: RX_FIFO overflow LINK_DIS: zero counter capacitor discharge mechanism LOCK_OUT: finish receiving a package LOCK_IN: start receiving a package
USB function interrupts: Endpoint 0 Interrupt Event: INT0RX: EP0 USB RX Event INT0TX: EP0 USB TX Event INT0IN: EP0 USB IN Token Event Endpoint X Interrupt Event: INT1: EP1 Interrupt INT2: EP2 Interrupt INT3: EP3 Interrupt Device State Interrupt Event: RSTINT: USB Bus Reset Event Detect IDLEINT: USB Bus Suspend Detect RUEINT: Enable USB Bus Resume Detect SOFINT: Start of Frame Interrupt
2.6 Baseband
Serial to Parallel conversion of RFW102 interface Input FIFO (RX_FIFO) Output FIFO (TX_FIFO) Preamble Correlation Packet Address Filter (Network and unique)
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
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EM77930
USB+BB Controller
CRC calculation Inter-RFWAVES networks Carrier-sense Discharge of RFW-102 reference capacitor Compensate for clock drifts between the transmitting EM77930 and the receiving EM77930 up to 1000ppm. Hence, the EM77930 requires low performance crystal Interrupt Driver
2.7 Universal Serial Bus (USB)
USB Specification Compliance
Conforms to USB specification, version 1.1 Conforms to USB Human Interface Device (HID) Specification, version 1.1.
5V supplied from PC USB interface
2.8 Pulse Width Modulation (PWM)
One Pulse Width Modulation (PWM) with 16-bit resolution
2.9 Built-in Voltage Regulator
Internal 3.3V regulator is used to be the power source of the MCU and the regulated output pin to provide a pull-up source for the external USB resistor on the downstream D- pin.
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Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
EM77930
USB+BB Controller
3 Pin Assignment
VDD
44 PA1 PA2 PA3 /RST PA4 PA5 PA6 PA7/PWM0 VSS D+ D1 2 3 4 5 6 7 8 9 10 11 12 VDD_5V
Fig. 3 Pad and Pins Configuration of EM77930
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
PA0
PD7
PD6
PD5
PD3
43
PF3 13 VDD
42
PF2 14 PB0
41
PF1 15 PB1
40
EM77930
PF0 16 PB2
PD4
39
38
37
36
35
34 33 32 31 30 29 28 27 26 25 24 23 PD2 PD1 PD0 OSCO2 OSCI VSS PLCC PC4/INT1 PC3/INT0 RFIO/PC6 TXRX/PC7
17 PB3
18 PB4
19 PB5
20 PB6
21 PB7
22
RF_ACT
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EM77930
USB+BB Controller
4 Pin Description
The Table below shows the corresponding relationship between the pad and pins of EM77930
Pin No. 1~3 4 5~8 11 9 10 11 12 13 14~21 22 23 24 25 26 27 28 29 30 31~ 38 39 40~43 44 Symbol PTA1~3 /RST PTA4~6 PWM0/PA7 VSS UPRT_D+ UPRT_DVDD_5V VDD KWU0~7 PB0~7 RF_ACT TXRX RFIO EINT0/ PC3 EINT1/ PC4 PLLC VSS OSCI OSCO2 PD0~7 VDD PF0 ~PF3 PA0 Type I/O - I/O I/O - - - - - I/O O O I/O I/O I/O - - I O I/O - I/O I/O Smitt Trigger - - - - - - - - - - - - - - - - - - - - - - Pull High /50K - - - - - - - - - - - - - Open Drain - - - - - - - - - - - - - - - - - - - - - - Function Description Pins 0~3 of Port A (default) Reset Pins 4~7 of Port A Pin 7 of Port A PWM0 output Ground Pin USB upstream differential data plus USB upstream differential data minus 5V Power supply for digital circuit and the embedded USB. 3.3v input. (no use regulator) 3.3v stable output. (use regulator) Pins 0~7 of Port B (default). Key Wake up 0~7 BB/RF Active Transceiver modes control Transceiver to/from RF modem External interrupt Pin 0 Pin 3 of Port C External interrupt Pin 1 Pin 4 of Port C External capacitor for PLL circuit Ground Pin Input of crystal oscillator Selected PLL Clock Output Pins 0~7 of Port D 3.3v input. Pins 0 ~ 3 of Port F Pin 0 of Port A
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Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
EM77930
USB+BB Controller
5
Block Diagram
ROM MCU RAM
I/O Port USB Device
OSCO RF Module BB PWM
PLL
Timer
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
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EM77930
USB+BB Controller
6
Memory
6.1 Program Memory
The EM77930 has a 14-bit program counter (PC). The program memory space, which is partitioned into two pages can address up to 12K. The first page has 8K and the second page has 4K in length. Fig. 6-1 depicts the profile of the program memory and stack. The initial Address is 0x0000. The table of the interrupt-vectors starts from 0x10 to 0xA8 with every other eight-address space.
HPC LPC A9 A8 A7~A0 RET RETL RETI INT CALL Stack 0 Stack 1
A13
A12
A11
A10
PS0 0 1
Address 0000 ~ 1 FFF 2000 ~ 2 FFF
Page 0 1 Stack 1E Stack 1F ACC2 ACC1 ACC0 SR2 SR1 SR0 RAMBS02 RAMBS01 RAMBS00 ROMPS2 ROMPS1 ROMPS0
Addr 0000
Vector Reset
0010
Key Wake-up
0020 0028
TCCOF FRCOF
Fig. 6-1 Configuration of Program Memory (ROM) for EM77930
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Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
EM77930
USB+BB Controller
6.2 RAM-Register
A total of 1218 accessible bytes of data memory are available for the EM77930. By function, they are classified into general purpose registers, system control / configuration registers, specification purpose registers, USB control/status registers, baseband (BB) control/status registers, timer/counter registers, and I/O port status/control registers. All of the above registers except I/O ports and their related control registers are implemented as static RAM. The RAM configurations are shown in Fig. 6-2.
00
System , Configuration, Clock , IOport Registers 30 31 General purpose registers 3F 40
000
001
010
011
100
101
00 EndPoint0 RXBuffer 3F 00 EndPoint0 TXBuffer 3F
00 EndPoint1 Buffer 3F 00 EndPoint2 Buffer 3F 00 EndPoint3 Buffer 3F 2FF 3FF 4FF 5FF General purpose Registers Of Bank 2 General purpose Registers Of Bank 3 General purpose Registers Of Bank 4 General purpose Registers Of Bank 5
80 Peripherals, and Interrupts Control registers 9A 9B General purpose Registers Of Bank 0 FF
180 General purpose Registers Of Bank 1 1CB 1CC USB Status Interrupts Control registers 1FF
280
380
480
580
Dual Port Register
7F
Fig. 6-2 Configuration of Data Memory (RAM) for EM77930
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
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EM77930
USB+BB Controller
The table is a summary of all registers except general purpose registers.
Addr Name Reset Type
Full Name Bit Name 0x00 IAC0 Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name 0x01 HPC Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name 0x02 LPC Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name 0x03 SR Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name 0x04 RAMBS0 Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name 0x05 ROMPS Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int RST R/W 0 P P PCF R/W 0 0 PCE R/W 0 0 PC7 R 0 0 PC6 R 0 0 IAC07 R/W 0 0 P IAC06 R/W 0 0 P
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Indirect Addressing Register contents IAC05 R/W 0 0 P IAC04 R/W 0 0 P IAC03 R/W 0 0 P IAC02 R/W 0 0 P IAC01 R/W 0 0 P IAC00 R/W 0 0 P
Most Significant Byte of Programming Counter PC5 R 0 0 PC4 R 0 0 PC3 R 0 0 PC2 R 0 0 PC1 R 0 0 PC0 R 0 0
Jump to the corresponding interrupt vector or continue to execute next instruction Least Significant Byte of Programming Counter PCD R/W 0 0 PCC R/W 0 0 PCB R/W 0 0 PCA R/W 0 0 PC9 R/W 0 0 PC8 R/W 0 0
Jump to the corresponding interrupt vector or continue to execute next instruction Status Register T R/W 1 T T P R/W 1 T T Z R/W U P P DC R/W U P P C R/W U P P
RAM Bank Select 0 RBS02 R/W 0 0 P RBS01 R/W 0 0 P RBS00 R/W 0 0 P
ROM Page Select RPS0 R/W 0 0 P
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Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
EM77930
USB+BB Controller
Addr
Name
Reset Type
Full Name Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Indirect Addressing Pointer 0 IAP07 R/W 0 0 P IAP06 R/W 0 0 P IAP05 R/W 0 0 P IAP04 R/W 0 0 P IAP03 R/W 0 0 P IAP02 R/W 0 0 P IAP01 R/W 0 0 P IAP00 R/W 0 0 P
0x06
IAP0
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
RAM Bank Select 1 RBS12 R/W 0 0 P RBS11 R/W 0 0 P RBS10 R/W 0 0 P
0x07
RAMBS1
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Indirect Addressing Pointer 1 IAP17 R/W 0 0 P IAP16 R/W 0 0 P IAP15 R/W 0 0 P IAP14 R/W 0 0 P IAP13 R/W 0 0 P IAP12 R/W 0 0 P IAP11 R/W 0 0 P IAP10 R/W 0 0 P
0x08
IAP1
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Indirect Addressing Contents 1 IAC17 R/W 0 0 P IAC16 R/W 0 0 P IAC15 R/W 0 0 P IAC14 R/W 0 0 P IAC13 R/W 0 0 P IAC12 R/W 0 0 P IAC11 R/W 0 0 P IAC10 R/W 0 0 P
0x09
IAC1
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Indirect Address Pointer Direction Control Register IAP1_D
IAP0_D IAP1_D_E IAP0_D_E R/W 0 0 P R/W 0 0 P R/W 0 0 P
0x0A
IAPDR
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
R/W 0 0 P
Least Significant Byte of Table Lookup TBL7 R/W 0 0 P TBL6 R/W 0 0 P TBL5 R/W 0 0 P TBL4 R/W 0 0 P TBL3 R/W 0 0 P TBL2 R/W 0 0 P TBL1 R/W 0 0 P TBL0 R/W 0 0 P
0x0B
LTBL
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
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EM77930
USB+BB Controller
Addr
Name
Reset Type
Full Name Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Indirect Addressing Pointer 0 IAP07 R/W 0 0 P IAP06 R/W 0 0 P IAP05 R/W 0 0 P IAP04 R/W 0 0 P IAP03 R/W 0 0 P IAP02 R/W 0 0 P IAP01 R/W 0 0 P IAP00 R/W 0 0 P
0x06
IAP0
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
RAM Bank Select 1 RBS12 R/W 0 0 P RBS11 R/W 0 0 P RBS10 R/W 0 0 P
0x07
RAMBS1
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Indirect Addressing Pointer 1 IAP17 R/W 0 0 P IAP16 R/W 0 0 P IAP15 R/W 0 0 P IAP14 R/W 0 0 P IAP13 R/W 0 0 P IAP12 R/W 0 0 P IAP11 R/W 0 0 P IAP10 R/W 0 0 P
0x08
IAP1
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Indirect Addressing Contents 1 IAC17 R/W 0 0 P IAC16 R/W 0 0 P IAC15 R/W 0 0 P IAC14 R/W 0 0 P IAC13 R/W 0 0 P IAC12 R/W 0 0 P IAC11 R/W 0 0 P IAC10 R/W 0 0 P
0x09
IAC1
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Indirect Address Pointer Direction Control Register IAP1_D
IAP0_D IAP1_D_E IAP0_D_E R/W 0 0 P R/W 0 0 P R/W 0 0 P
0x0A
IAPDR
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
R/W 0 0 P
Least Significant Byte of Table Lookup TBL7 R/W 0 0 P TBL6 R/W 0 0 P TBL5 R/W 0 0 P TBL4 R/W 0 0 P TBL3 R/W 0 0 P TBL2 R/W 0 0 P TBL1 R/W 0 0 P TBL0 R/W 0 0 P
0x0B
LTBL
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int
12 *
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
EM77930
USB+BB Controller
Addr
Name
Reset Type
Full Name Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Most Significant Byte of Table Lookup TBLF R/W 0 0 P TBLE R/W 0 0 P TBLD R/W 0 0 P TBLC R/W 0 0 P TBLB R/W 0 0 P TBLA R/W 0 0 P TBL9 R/W 0 0 P TBL8 R/W 0 0 P
0x0C
HTBL
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Stack Pointer STKPT7 STKPT6 STKPT5 STKPT4 STKPT3 STKPT2 STKPT1 STKPT0 R 1 1 P R 1 1 P R 1 1 P R 1 1 P R 1 1 P R 1 1 P R 1 1 P R 1 1 P
0x0D
STKPTR
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Repeat Pointer RPTC7 R/W 0 0 P RPTC6 R/W 0 0 P RPTC5 R/W 0 0 P RPTC4 R/W 0 0 P RPTC3 R/W 0 0 P RPTC2 R/W 0 0 P RPTC1 R/W 0 0 P RPTC0 R/W 0 0 P
0x0E
RPTC
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
No Connection -
0x0F
NC
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Time Clock/Counter TCC7 R/W 0 0 0 TCC6 R/W 0 0 0 TCC5 R/W 0 0 0 TCC4 R/W 0 0 0 TCC3 R/W 0 0 0 TCC2 R/W 0 0 0 TCC1 R/W 0 0 0 TCC0 R/W 0 0 0
0x10
TCC
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Interrupt Flag PWM0IF R/W 0 0 P EINT1F R/W 0 0 P EINT0F R/W 0 0 P TCCOF R/W 0 0 P FRCOF R/W 0 0 P
0x11
INTF
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
* 13
EM77930
USB+BB Controller
Addr
Name
Reset Type
Full Name Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port A Key Wake-up Interrupt Flag KWU3IF KWU2IF KWU1IF KWU0IF R/W 0 0 0 R/W 0 0 0 R/W 0 0 0 R/W 0 0 0
0x12
KWUAIF
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Port B Key Wake-up Interrupt Flag KWU7IF KWU6IF KWU5IF KWU4IF KWU3IF KWU2IF KWU1IF KWU0IF R/W 0 0 0 R/W 0 0 0 R/W 0 0 0 R/W 0 0 0 R/W 0 0 0 R/W 0 0 0 R/W 0 0 0 R/W 0 0 0
0x13
KWUBIF
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
General Purpose I/O port, Port A PA7 R/W U U P PA6 R/W U U P PA5 R/W U U P PA4 R/W U U P PA3 R/W U U P PA2 R/W U U P PA1 R/W U U P PA0 R/W U U P
0x14
PA
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
General Purpose I/O port, Port B PB7 R/W U U P PB6 R/W U U P PB5 R/W U U P PB4 R/W U U P PB3 R/W U U P PB2 R/W U U P PB1 R/W U U P PB0 R/W U U P
0x15
PB
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
General Purpose I/O port, Port C PTC4 R/W U U P PTC3 R/W U U P -
0x16
PC
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
General Purpose I/O port, Port D PD7 R/W U U P PD6 R/W U U P PD5 R/W U U P PD4 R/W U U P PD3 R/W U U P PD2 R/W U U P PD1 R/W U U P PD0 R/W U U P
0x17
PD
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int
14 *
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
EM77930
USB+BB Controller
Addr
Name
Reset Type
Full Name Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
No Connection -
0x18
NC
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
General Purpose I/O port, Port F PTF3 R/W U U P PTF2 R/W U U P PTF1 R/W U U P PTF0 R/W U U P
0x19
PF
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Least Significant Byte of the 16-bit Free Run Counter FRC7 R 0 0 0 FRC6 R 0 0 0 FRC5 R 0 0 0 FRC4 R 0 0 0 FRC3 R 0 0 0 FRC2 R 0 0 0 FRC1 R 0 0 0 FRC0 R 0 0 0
0x1A
LFRC
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Most Significant Byte of 16-bit Free Run Counter FRCF R/W 0 0 0 FRCE R/W 0 0 0 FRCD R/W 0 0 0 FRCC R/W 0 0 0 FRCB R/W 0 0 0 FRCA R/W 0 0 0 FRC9 R/W 0 0 0 FRC8 R/W 0 0 0
0x1B
HFRC
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Least Significant Byte Buffer of the 16-bit Free Run Counter FRCB7 R/W 0 0 0 FRCB6 R/W 0 0 0 FRCB5 R/W 0 0 0 FRCB4 R/W 0 0 0 FRCB3 R/W 0 0 0 FRCB2 R/W 0 0 0 FRCB1 R/W 0 0 0 FRCB0 R/W 0 0 0
0x1C
LFRCB
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
No Connection -
0x1D
NC
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
* 15
EM77930
USB+BB Controller
Addr
Name
Reset Type
Full Name Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
No Connection -
0x1E
NC
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
No Connection -
0x1F
NC
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
LSB Converting Value of ADC -
0x20
NC
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Duty of PWM-Low Byte DT07 R 0 0 P DT06 R 0 0 P DT05 R 0 0 P DT04 R 0 0 P DT03 R 0 0 P DT02 R 0 0 P DT01 R 0 0 P DT00 R 0 0 P
0x21
DT0L
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Duty of PWM-High Byte DT0F R 0 0 P DT0E R 0 0 P DT0D R 0 0 P DT0C R 0 0 P DT0B R 0 0 P DT0A R 0 0 P DT09 R 0 0 P DT08 R 0 0 P
0x22
DT0H
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Period of PWM - Low Byte PRD07 R/W 0 0 P PRD06 R/W 0 0 P PRD05 R/W 0 0 P PRD04 R/W 0 0 P PRD03 R/W 0 0 P PRD02 R/W 0 0 P PRD01 R/W 0 0 P PRD00 R/W 0 0 P
0x23
PRD0L
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int
16 *
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
EM77930
USB+BB Controller
Addr
Name
Reset Type
Full Name Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Period of PWM- High Byte PRD0F R/W 0 0 P PRD0E R/W 0 0 P PRD0D R/W 0 0 P PRD0C R/W 0 0 P PRD0B R/W 0 0 P PRD0A R/W 0 0 P PRD09 R/W 0 0 P PRD08 R/W 0 0 P
0x24
PRD0H
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Duty Latch of PWM-Low Byte DL07 R/W 0 0 P DL06 R/W 0 0 P DL05 R/W 0 0 P DL04 R/W 0 0 P DL03 R/W 0 0 P DL02 R/W 0 0 P DL01 R/W 0 0 P DL00 R/W 0 0 P
0x25
DL0L
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Duty Latch of PWM-High Byte DL0F R/W 0 0 P DL0E R/W 0 0 P DL0D R/W 0 0 P DL0C R/W 0 0 P DL0B R/W 0 0 P DL0A R/W 0 0 P DL019 R/W 0 0 P DL08 R/W 0 0 P
0x26
DL0H
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
No Connection -
0x27
NC
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
No Connection -
0x28
NC
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
No Connection -
0x29
NC
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
* 17
EM77930
USB+BB Controller
Addr
Name
Reset Type
Full Name Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
No Connection -
0x2A
NC
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
No Connection -
0x2B
NC
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
No Connection -
0x2C
NC
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
BB Address Register AAR4 R/W 0 0 P AAR3 R/W 0 0 P AAAR2 R/W 0 0 P AAR1 R/W 0 0 P AAR0 R/W 0 0 P
0x2D
RFAAR
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
BB Data Buffer RFDB7 R/W 0 0 P RFDB6 R/W 0 0 P RFDB5 R/W 0 0 P RFDB4 R/W 0 0 P RFDB3 R/W 0 0 P RFDB2 R/W 0 0 P RFDB1 R/W 0 0 P RFDB0 R/W 0 0 P
0x2E
RFDB
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
BB Data Read/Write Control Register RRST R/W 0 0 P RFRD R/W 1 1 P RFWR R/W 1 1 P
0x2F
RFACR
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int
18 *
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
EM77930
USB+BB Controller
Addr
Name
Reset Type
Full Name Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BB Interrupt Flag Register CSDF R/W 0 0 P TX_AEF RX_AFF TX_EMPTYF RX_OFF LINK_ DISF LOCK_OUTF LOCK_ INF R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P
0x30
RFINTF
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Dual Port Registers (64 in total) DPR7 R/W X X P DPR6 R/W X X P DPR5 R/W X X P DPR4 R/W X X P DPR3 R/W X X P DPR2 R/W X X P DPR1 R/W X X P DPR0 R/W X X P
0x40 ~ 0x7F DPR
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Peripheral Function Enable USBE R/W 0 0 P WME R/W 0 0 P PWME R/W 0 0 P TCCE R/W 0 0 P FRCE R/W 0 0 P
0x80
PRIE
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Interrupt Enable Control Register GIE R/W 0 0 P PWM0IE R/W 0 0 P EINT1E R/W 0 0 P EINT0E R/W 0 0 P TCCOE R/W 0 0 P FRCOE R/W 0 0 P
0x81
INTE
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
No Connection -
0x82
NC
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
No Connection -
0x83
NC
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
* 19
EM77930
USB+BB Controller
Addr
Name
Reset Type
Full Name Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
External Interrupt Edge Control SYNB2 R/W 0 0 P SYNB1 R/W 0 0 P SYNB0 R/W 0 0 P EINT1ED EINT0ED R/W 0 0 P R/W 0 0 P
0x84
EINTED
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
No Connection -
0x85
SPIC
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
I/O Control of Port A IOCA7 R/W 1 1 P IOCA6 R/W 1 1 P IOCA5 R/W 1 1 P IOCA4 R/W 1 1 P IOCA3 R/W 1 1 P IOCA2 R/W 1 1 P IOCA1 R/W 1 1 P IOCA0 R/W 1 1 P
0x86
IOCA
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
I/O Control of Port B IOCB7 R/W 1 1 P IOCB5 R/W 1 1 P IOCB5 R/W 1 1 P IOCB4 R/W 1 1 P IOCB3 R/W 1 1 P IOCB2 R/W 1 1 P IOCB1 R/W 1 1 P IOCB0 R/W 1 1 P
0x87
IOCB
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
I/O Control of Port C IOCC4 R/W 1 1 P IOCC3 R/W 1 1 P -
0x88
IOCC
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
I/O Control of Port D IOCD7 R/W 1 1 P IOCD6 R/W 1 1 P IOCD5 R/W 1 1 P IOCD4 R/W 1 1 P IOCD3 R/W 1 1 P IOCD2 R/W 1 1 P IOCD1 R/W 1 1 P IOCD0 R/W 1 1 P
0x89
IOCD
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int
20 *
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
EM77930
USB+BB Controller
Addr
Name
Reset Type
Full Name Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
No Connection -
0x8A
NC
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
I/O Control of Port F IOCF3 R/W 1 1 P IOCF2 R/W 1 1 P IOCF1 R/W 1 1 P IOCF0 R/W 1 1 P
0x8B
IOCF
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Pull-up control of Port A PUCA7 R/W 0 0 P PUCA6 R/W 0 0 P PUCA5 R/W 0 0 P PUCA4 R/W 0 0 P PUCA3 R/W 0 0 P PUCA2 R/W 0 0 P PUCA1 R/W 0 0 P PUCA0 R/W 0 0 P
0x8C
PUCA
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Pull-up control of Port B PUCB7 R/W 0 0 P PUCB6 R/W 0 0 P PUCB5 R/W 0 0 P PUCB4 R/W 0 0 P PUCB3 R/W 0 0 P PUCB2 R/W 0 0 P PUCB1 R/W 0 0 P PUCB0 R/W 0 0 P
0x8D
PUCB
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Pull-up control of Port C PUCC4 R/W 0 0 P PUCC3 R/W 0 0 P
0x8E
PUCC
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Pull-up control of Port D PUCD7 R/W 0 0 P PUCD6 R/W 0 0 P PUCD5 R/W 0 0 P PUCD4 R/W 0 0 P PUCD3 R/W 0 0 P PUCD2 R/W 0 0 P PUCD1 R/W 0 0 P PUCD0 R/W 0 0 P
0x8F
PUCD
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
* 21
EM77930
USB+BB Controller
Addr
Name
Reset Type
Full Name Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
No Connection -
0x90
NC
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Pull-up Control of Port F PUCF3 R/W 0 0 P PUCF2 R/W 0 0 P PUCF1 R/W 0 0 P PUCF0 R/W 0 0 P
0x91
PUCF
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Open Drain Control of Port B OPCB7 R/W 0 0 P OPCB6 R/W 0 0 P OPCB5 R/W 0 0 P OPCB4 R/W 0 0 P OPCB3 R/W 0 0 P OPCB2 R/W 0 0 0 OPCB1 R/W 0 0 0 OPCB0 R/W 0 0 0
0x92
ODCB
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Time Clock/Counter Control TCCS0 R/W 0 0 P PS2 R/W 0 0 P PS1 R/W 0 0 P PS0 R/W 0 0 P
0x93
TCCC
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Free Run Counter Control/OSCO2 Output Control OSC02E R/W 0 0 P OSCO2 SL1 R/W 0 0 P OSCO2 SL0 R/W 0 0 P PPSCL2 PPSCL1 PPSCL0 R/W 0 0 P R/W 0 0 P R/W 0 0 P FRCCS R/W 0 0 P
0x94
FRCC
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Watchdog Timer Control GREEN R/W 0 0 0 WDTCE R/W 0 0 P RAT2 R/W 0 0 P RAT1 R/W 0 0 P RAT0 R/W 0 0 P
0x95
WDTC
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int
22 *
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
EM77930
USB+BB Controller
Addr
Name
Reset Type
Full Name Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
No Connection -
0x96
NC
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
No Connection -
0x97
NC
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
PWM Control Register S_PWM0 R/W 0 0 P -
0x98
PWMCR
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
BB Interrupt Enable Control Register CSDE R/W 0 0 P TX_AEE RX_AFE TX_ EMPTYE RX_OFE LINK_ DISE LOCK_OUTE LOCK_ INE R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P
0x99
RFINTE
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int
Reserved 0x1CC Full Name Bit Name 0x1CD GCNTR Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int -
USB General Control Register RESUME SUSPEND R/W 0 0 P R/W 0 0 P PLUG R/W 0 0 P URST R/W 0 0 P
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
* 23
EM77930
USB+BB Controller
Addr
Name
Reset Type
Full Name Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
End Point 1 Control Register EP1EN R/W 0 0 P EP1DIR R/W 1 1 P EP1TP1 R/W 0 0 P EP1TP0 R/W 0 0 P
0x1CE
EP1CNTR
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
End Point 2 Control Register EP2EN R/W 0 0 P EP2DIR R/W 1 1 P EP2TP1 R/W 0 0 P EP2TP0 R/W 0 0 P
0x1CF EP2CNTR
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
End Point 3 Control Register EP3EN R/W 0 0 P EP3DIR R/W 1 1 P EP3TP1 R/W 0 0 P EP3TP0 R/W 0 0 P
0x1D0 EP3CNTR
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Endpoint Interrupt Event Status Register INT3 R/W 0 0 P INT2 R/W 0 0 P INT1 R/W 0 0 P INT0IN R/W 1 1 P INT0TX R/W 0 0 P INT0RX R 0 0 P
0x1D1 EPINTR
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Endpoint Interrupt Event Enable Control Register INT3E R/W 0 0 P INT2E R/W 0 0 P INT1E R/W 0 0 P INT0INE INT0TXE INT0RXE R/W 0 0 P R/W 0 0 P R/W 0 0 P
0x1D2 EPINTE
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
State Interrupt Event Flag Register FRWPINT RUEINT IDLEINT R/W 0 0 P R/W 0 0 P R/W 0 0 P RSTINT R/W 0 0 P
0x1D3 STAINTR
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int
24 *
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
EM77930
USB+BB Controller
Addr
Name
Reset Type
Full Name Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
State Interrupt Event Enable Control Register FRWPINTE RUEINTE IDLEINTE RSTINTE R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P
0x1D4 STAINTE
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Function Address FADDR6 FADDR5 FADDR4 FADDR3 FADDR2 FADDR1 FADDR0 R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P
0x1D5 FAR
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Endpoint 0 RX Token USETUPOW USETUP
UOUT R/W 0 0 P
0x1D6 EP0RXTR
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
R/W 0 0 P
R/W 0 0 P
Endpoint 0 RX Command/Status
CDTOG0RX ERRSTS0RX STALLST S0RX ACKSTS0RX DT E R RX DTOG0RX SESTALL0RX RXEN0RX OG R 0
0x1D7 EP0RXCSR
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
W 0 0 P
R 0 0 P
R 0 0 P
R 0 0 P
R 0 0 P
R 0 0 P
R/W 1 1 P
R/W 1 1 P
Endpoint 0 TX Command/Status
CDTOG0TX ERRSTS0TX ST ALLST S0TX ACKSTS0TX
-
DTOG0TX SESTALL0TX TXEN0TX
0x1D8 EP0TXCSR
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
W 0 0 P
R 0 0 P
R 0 0 P
R 0 0 P
R 1 1 P
R/W 1 1 P
R/W 0 0 P
Endpoint 1 Command/Status CDTOG1 ERRSTS1 STALLSTS1 ACKSTS1 DTOGERR1 DTOG1 SESTALL1 RXTXEN1 W 0 0 P R 0 0 P R 0 0 P R 0 0 P R 0 0 P R 0 0 P R/W 1 1 P R/W 0 0 P
0x1D9 EP1CSR
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
* 25
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USB+BB Controller
Addr
Name
Reset Type
Full Name Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Endpoint 2 Command/Status CDTOG2 ERRSTS2 STALLSTS2 ACKSTS2 DTOGERR2 DTOG2 W 0 0 P R 0 0 P R 0 0 P R 0 0 P R 0 0 P R 0 0 P SESTALL2 RXTXEN2 R/W 1 1 P R/W 0 0 P
0x1DA
EP2CSR
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Endpoint 3 Command/Status CDTOG3 ERRSTS3 STALLSTS3 ACKSTS3 DTOGERR3 DTOG3 W 0 0 P R 0 0 P R 0 0 P R 0 0 P R 0 0 P R 0 0 P SESTALL3 RXTXEN3 R/W 1 1 P R/W 0 0 P
0x1DB
EP3CSR
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Endpoint 0 RX Count EP0RXCT6 EP0RXCT5 EP0RXCT4 EP0RXCT3 EP0RXCT2 EP0RXCT1 EP0RXCT0 R 0 0 P R 0 0 P R 0 0 P R 0 0 P R 0 0 P R 0 0 P R 0 0 P
0x1DC
EP0RXCTR
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Endpoint 0 TX Count EP0TXCT6 EP0TXCT5 EP0TXCT4 EP0TXCT3 EP0TXCT2 EP0TXCT1 EP0TXCT0 R 0 0 P R 0 0 P R 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P
0x1DD
EP0TXCTR
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Endpoint 1 Count EP1CT6 EP1CT5 EP1CT4 EP1CT3 EP1CT2 EP1CT1 EP1CT0 R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P
0x1DE
EP1CTR
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Endpoint 2 Count EP2CT6 EP2CT5 EP2CT4 EP2CT3 R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P EPCT2 R/W 0 0 P EP2CT1 EP2CT0 R/W 0 0 P R/W 0 0 P
0x1DF EP2CTR
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int
26 *
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
EM77930
USB+BB Controller
Addr
Name
Reset Type
Full Name Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Endpoint 3 Count EP3CT6 EP3CT5 EP3CT4 EP3CT3 EP3CT2 EP3CT1 EP3CT0 R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P
0x1E0 EP3CTR
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Endpoint 0 RX Data EP0RX7 EP0RX6 EP0RX5 EP0RX4 EP0RX3 EP0RX2 EP0RX1 EP0RX0 R 0 0 P R 0 0 P R 0 0 P R 0 0 P R 0 0 P R 0 0 P R 0 0 P R 0 0 P
0x1E1
EP0RXD Read/Write (R/W) AR Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Endpoint 0 TX Data EP0TX7 W 0 0 P EP0TX6 W 0 0 P EP0TX5 W 0 0 P EP0TX4 W 0 0 P EP0TX3 W 0 0 P EP0TX2 W 0 0 P EP0TX1 W 0 0 P EP0TX0 W 0 0 P
0x1E2
EP0TXD AR
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Endpoint 1 Data EP1D7 R/W 0 0 P EP1D6 R/W 0 0 P EP1D5 R/W 0 0 P EP1D4 R/W 0 0 P EP1D3 R/W 0 0 P EP1D2 R/W 0 0 P EP1D1 R/W 0 0 P EP1D0 R/W 0 0 P
0x1E3 EP1DAR
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Endpoint 2 Data EP2D7 R/W 0 0 P EP2D6 R/W 0 0 P EP2D5 R/W 0 0 P EP2D4 R/W 0 0 P EP2D3 R/W 0 0 P EP2D2 R/W 0 0 P EP2D1 R/W 0 0 P EP2D0 R/W 0 0 P
0x1E4 EP2DAR
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Endpoint 3 Data EP3D7 R/W 0 0 P EP3D6 R/W 0 0 P EP3D5 R/W 0 0 P EP3D4 R/W 0 0 P EP3D3 R/W 0 0 P EP3D2 R/W 0 0 P EP3D1 R/W 0 0 P EP3D0 R/W 0 0 P
0x1E5 EP3DAR
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
* 27
EM77930
USB+BB Controller
Addr
Name
Reset Type
Full Name Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved -
0x1E6 HGSR
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Hub Interrupt Event Flag Register
SOFINT
-
-
-
-
-
-
0x1E7 HINTR
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
-
R/W 0 0 P
Hub Interrupt Event Enable Control Register
-
SOFINTE R/W 0 0 P
-
Reserved
-
-
-
-
0x1E8 HINTE
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
-
-
-
-
-
-
-
-
-
0x1E9 ~ 0x1FD
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Least Significant Byte of the Frame Number FN7 R 0 0 P FN6 R 0 0 P FN5 R 0 0 P FN4 R 0 0 P FN3 R 0 0 P FN2 R 0 0 P FN1 R 0 0 P FN0 R 0 0 P
0x1FE FNLR
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Most Significant Byte of the Frame Number FNA R 0 0 P FN9 R 0 0 P FN8 R 0 0 P
0x1FF FNHR
Read/Write (R/W) Power-on /RESET and WDT Wake-up from Int
28 *
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
EM77930
USB+BB Controller
7
Function Description
7.1 Special Purpose Registers
The special purpose registers are function-oriented registers used by the CPU to access memory, record execution results, and carry out the desired operation. The functions of the registers related to the core are described in the following subsections
7.1.1 Accumulator - ACC
Internal data transfer operation, or instruction operand holding usually involves the temporary storage function of the Accumulator, which is not an addressable register.
7.1.2 Indirect Addressing Contents - IAC0 (0x00) and IAC1 (0x09)
The contents of R0 and R9 are implemented as indirect addressing pointers if any instruction uses R6 and R8 as registers.
7.1.3 Program Counter HPC (0x01) and LPC (0x02)
The Program Counter (PC) is composed of registers HPC and LPC. The PC and the hardware stacks are 14 bits wide. The structure is depicted in Fig. 6-1. Generates 12K x 16 on-chip ROM addresses to the corresponding program memory (ROM). All the bits of PC are set to "0"s as a reset condition occurs. "RET" ("RETL k", "RETI") instruction loads the program counter with the contents at the top of the stack. "MOV R2, A" allows the loading of an address from the "A" register to the lower 8 bits of the PC, and the high byte (A8~A14) of the PC remain unchanged. "ADD R2, A" & "TBL" allows a corresponding address / offset to be added to the current PC.
7.1.4 Status Register -SR (0x03)
Bit 7 Bit 6 Bit 5 RST Bit 4 T Bit 3 P Bit 2 Z Bit 1 DC Bit 0 C
Bit 0 (C): Carry flag. This bit indicates that a carry out of ALU occurred during the last arithmetic operation. This bit is also affected during bit test, branch instruction and during bit shifts. Bit 1 (DC): Auxiliary carry flag. This bit is set during ADD and ADC operations to indicate that a carry occurred between Bit 3 and Bit 4.
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
* 29
EM77930
USB+BB Controller Bit 2 (Z): Zero flag. Set to "1" if the result of the last arithmetic, data or logic operation is zero. Bit 3 (P): Power down bit. Set to 1 during power on or by a "WDTC" command and reset to 0 by a "SLEP" command. Bit 4 (T): Time-out bit. Set to 1 by the "SLEP" command and the "WDTC" command, or during power up and reset to 0 by WDT timeout. Bit 5 (RST): Set if the CPU wakes up by keying on the wake-up pins. Reset if the chip wakes up through other ways. Bits 6 and 7 are reserved.
7.1.5 RAM Bank Selector - RAMBS0 (0x04) and RAMBS1 (0x07)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 RAMBSX2 Bit 1 RAMBSX1 Bit 0 RAMBSX0
As depicted in Fig. 6-2, there are six available banks in the MCU. Each of them has 128 registers and can be accessed by defining the bits, RAMBSX0 ~ RAMBSX2, as shown below.
RAMBSX (0x04/0x07) 000 001 010 011 100 101 Bank 0 1 2 3 4 5
7.1.6 ROM Page Selector - ROMPS (0x05)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RPS0
As depicted in Fig. 6-1, there are two available pages in MCU. The first page has 8K*16 ROM size and the second page has 4Kx16 ROM size. Both of them can be accessed by defining the bits, RPS0, as shown below.
RPS0 0 1 Page (Address) 0 (0x0000~0x1FFF) 1 (0x2000~0x2FFF)
7.1.7 Indirect Addressing Pointers - IAP0 (0x06), and IAP1 (0x08)
Both R6 and R8 are not physically implemented registers. They are useful as indirect addressing pointers. Any instruction using R6/R4 and R8/R7 as registers actually access data pointed by R0 and R9 individually.
30 * Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
EM77930
USB+BB Controller
7.1.8 Indirect Address Pointer Direction Control Register - IAPDR (0x0A)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 IAP1_D Bit 2 Bit 1 Bit 0 IAP0_D IAP1_D_E IAP0_D_E
Bit 0/1 (IAP0_D_E/IAP1_D_E) Indirect addressing Pointer 0/1 direction function enable bit. 0: Disable 1: Enable Bit 2/3 (IAP0_D/IAP1_D) Indirect addressing pointer0/1 direction control bit. 0: Minus direction 1: Plus direction
7.1.9 Table Look-up Pointers - LTBL (0x0B), and HTBL (0x0C)
The maximum length of a table is 64K, and can be accessed through registers LTBL and HTBL. HTBL is the high byte of the pointer, whereas LTBL is the low byte.
7.1.10 Stack Pointer - STKPTR (0x0D)
Register RD indicates how many stacks the current free run program uses. It is a read only register.
7.1.11 Repeat Counter - RPTC (0x0E)
The RE register is used to set how many times the "RPT" instruction is going to read the table.
7.1.12 Real Time Clock Counter - RTCC (0x10)
TCC counter.
7.1.13 Interrupt Flag Register - INTF (0x11)
Bit 7 Bit 6 Bit 5 Bit 4 PWM0IF Bit 3 EINT1F Bit 2 EINT0F Bit 1 TCCOF Bit 0 FRCOF
Bit 0 (FRCOF):
FRC Overflow interrupt. Set as the contents of the FRC counter change from 0xFFFF to 0x0000, reset by software. TCC Overflow interrupt. Set as the contents of the TCC counter change from 0xFF to 0x00, reset by software.
Bit 1 (TCCOF):
Bits 2 ~ 3 (EINT0F & EINTIF): External input pin interrupt flag. Interrupt occurs at the defined edge of the external input pin, reset by software.
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
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USB+BB Controller
Bit 4 (PWM0IF): PWM interrupt flag. Interrupt occurs when TMRX is equal to PRDX, reset by software. Bits 5 ~ 7 reserved Each bit can function independently regardless whether its related interrupt mask bit is enabled or not. Each bit can function independently no matter its related interrupt mask bit is enabled or not.
7.1.14 Key Wake-up Flag Register - KWUAIF (0x12) and KWUBIF (0x13)
KWUAIF: Port A Key Wake-up Interrupt Flag
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 KWUBIF Bit 2 KWUAIF Bit 1 KWU9IF Bit 0 KWU8IF
KWUBIF: Port B Key Wake-up Interrupt Flag
Bit 7 KWU7IF Bit 6 KWU6IF Bit 5 KWU5IF Bit 4 KWU4IF Bit 3 KWU3IF Bit 2 KWU2IF Bit 1 KWU1IF Bit 0 KWU0IF
7.1.15 I/O Port Registers - PTA ~ PTF (0x14 ~ 0x19)
PTX can be operated as any other general purpose registers by related instructions. That is, PTX is an 8-bit, bi-directional, general purpose port. Its corresponding IO control bit determines the data direction of a PTX pin.
7.1.16 16-bit Free Run Counter (FRC) - LFRC (0x1A) HFRC (0x1B) and LFRCB (0x1C)
R1A is a 16-bit FRC low byte; R1B is high byte; R1C is a low byte buffer.
7.1.17 PWM Duty - DT0L (0x21)/DT0H (0x22)
R22:R21 16-bit PWM0 output duty cycle.
7.1.18 PWM Period - PRD0L (0x23)/PRD0H (0x24)
R24:R23 16-bit PWM output period cycle.
7.1.19 PWM Duty Latch - DL0L (0x25)/DL0H (0x26)
R26:R25 16-bit PWM output duty cycle buffer.
7.1.20 BB Address Register - RFAAR (0x2D)
Register R2D indicates BB indirect RAM address.
7.1.21 BB Data Buffer Register - RFDB (0x2E)
Register R2E indicates BB indirect RAM data.
32 * Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
EM77930
USB+BB Controller
7.1.22 BB Data Read/Write Control Register - RFACR (0x2F)
Register R2F indicates WM RAM access control.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 RRST Bit 1 RFRD Bit 0 RFWR
Bit 0 (RFWR): Bit 1 (RFRD): Bit 2 (RRST):
Write BB register Read BB register BB S/W reset
Bit 3~Bit 7: reserved
7.1.23 BB Interrupt Flag Register - RFINTF (0x30)
Bit 7 CSDF Bit 6 TX_AEF Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RX_AFF TX_ EMPTYF RX_OFF LINK_ DISF
LOCK_OUTF LOCK_ INF
Bit 0 (LOCK_INF):
This bit reflects the LOCK IN flag interrupt.
Bit 1 (LOCK_OUTF): This bit reflects the LOCK OUT flag interrupt. Bit 2 (LINK_DISF): This interrupt is invoked by the zero counter capacitor discharge mechanism. Bit 3 (RX_OFF): This bit reflects the RX FIFO full flag interrupt.
Bit 4 (TX_EMPTYF): This bit reflects the TX EMPTY flag interrupt. Bit 5 (RX_AFF): Bit 6 (TX_AEF): Bit 7 (CSDF): This bit reflects the RX FIFO almost full flag interrupt. This bit reflects the TX FIFO almost empty flag interrupt. This flag indicates that a carrier-sense interrupt has occurred.
7.2 Dual Port Register (0x40 ~ 0x7F)
R 40 ~ R7F are dual port register.
7.3 System Status, Control and Configuration Registers
These registers are function-oriented registers used by the CPU to record, enable or disable the peripheral modules, interrupts, and the operation clock modes.
7.3.1
Bit 7 -
Peripherals Enable Control - PRIE (0x80)
Bit 6 USBE Bit 5 BBE Bit 4 Bit 3 Bit 2 PWM0E Bit 1 TCCE Bit 0 FRCE
Bit 0 (FRCE): Bit 1 (TCCE):
Free Run Counter 0 (FRC0) Enable bit Timer Clock/Counter (TCC) Enable bit
Bit 2 (PWM0E): PWM0 function enable bit
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
* 33
EM77930
USB+BB Controller
Bit 5 (BBE): Bit 6 (USBE): Bits 3, 4, 7:
Base band (BB) Enable bit Universal Serial Bus (USB) Enable bit Reserved 0: disable function 1: enable function
7.3.2
Bit 7 GIE
Interrupts Enable Control - INTE (0x81)
Bit 6 Bit 5 Bit 4 PWM0IE Bit 3 EINT1E Bit 2 EINT0E Bit 1 TCCOE Bit 0 FRCOE
Bit 0 (FRC0OE): Bit 1 (TCCOE): Bit 2 (EINT0E): Bit 3 (EINT1E): Bit 4 (PWM0IE): Bits 5, 6:
Free Run Counter (FRC) Overflow interrupt enable bit. TCC (TCC) Overflow interrupt enable bit. External pin (EINT0) interrupt enable bit. External pin (EINT1) interrupt enable bit. PWM0 period complete enable bit. Reserved 0: disable function interrupt 1: enable function interrupt
Bit 7 (GIE):
Global interrupt control bit. Global interrupt is enabled by the ENI and RETI instructions and is disabled by the DISI instruction. 0: Global interrupt disable 1: Global interrupt enable
7.3.3
Key Wake-up Enable Control - KWUAIE (0x82) and KWUBIE (0x83)
Bit 6 Bit 5 Bit 4 Bit 3 KWUBE Bit 2 KWUAE Bit 1 KWU9E Bit 0 KWU8E
KWUAIE: Port A Key Wake-up Interrupt Enable Control Register
Bit 7 -
Bit 0 ~Bit 3 (KWU8E ~ KWUBE): Enable or disable the PTA0 ~ PTA3 Key Wake-up function. 0: disable key wake-up function 1: enable key wake-up function KWUBIE: Port B Key Wake-up Interrupt Enable Control Register
Bit 7 KWU7E Bit 6 KWU6E Bit 5 KWU5E Bit 4 KWU4E Bit 3 KWU3E Bit 2 KWU2E Bit 1 KWU1E Bit 0 KWU0E
Bit 0 ~Bit 7 (KWU0 ~ KWU7): Enable or disable the PTB0 ~ PTB7 Key Wake-up function. 0: disable key wake-up function 1: enable key wake-up function
34 * Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
EM77930
USB+BB Controller
7.3.4
Bit 7
External Interrupts Edge Control - EINTED (0x84)
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EINT1ED EINT0ED
Bit 0 (EINT0ED): Define which edge as an interrupt source for EINT0. Bit 1 (EINT1ED): Define which edge as an interrupt source for EINT1. 0: Falling Edge 1: Rising Edge Bit 2 ~ Bit 7: reserved
7.3.5
I/O Control Registers - IOCA~IOCF (0x86~0x8B)
OCX is used to determine the data direction of its corresponding I/O port bit. 0: configure a selected I/O pin as output 1: configure a selected I/O pin as input The only four least significant bits of Port F and the only five least significant bits of Port C are available
7.3.6
Pull-up Resistance Control Registers for Ports - PUCA~PUCF (0x8C ~ 0x91)
Each bit of PUCX is used to control the pull-up resistors attached to its corresponding pin respectively. The theoretical value of the resistor is 50 K. However, due to process variation, 35% variation in resistance must be taken into consideration. PUCX:
Bit 7 PUCX7 Bit 6 PUCX6 Bit 5 PUCX5 Bit 4 PUCX4 Bit 3 PUCX3 Bit 2 PUCX2 Bit 1 PUCX1 Bit 0 PUCX0
0: Pull-up Resistors disconnected 1: Pull-up Resistors attached
7.3.7
Open Drain Control Registers of Port B - ODCB (0x92)
ODCB: Open drain control of Port B.
Bit 7 OPCB7 Bit 6 OPCB6 Bit 5 OPCB5 Bit 4 OPCB4 Bit 3 OPCB3 Bit 2 OPCB2 Bit 1 OPCB1 Bit 0 OPCB0
0: Open drain disable 1: Open drain enable
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
* 35
EM77930
USB+BB Controller
7.3.8
Bit 7 -
Timer Clock Counter Controller - TCCC (0x93)
Bit 6 Bit 5 Bit 4 Bit 3 TCCS0 Bit 2 PSR2 Bit 1 PSR1 Bit 0 PSR0
Bits 0 ~ 2 (PSR0 ~ PSR2): Prescaler for TCC.
PSR2 0 0 0 0 1 1 1 1 PSR1 0 0 1 1 0 0 1 1 PSR0 0 1 0 1 0 1 0 1 Clock Rate 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256
Bit 3 (TCCS0): Clock Source Select
TCCS0 0 1 Clock Source Selected PLL Clock Source Selected IRC Clock Source
Bits 4 ~ 7: Reserved
7.3.9
Bit 7 -
Free Run Counter Controller - FRCC (0x94)
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 PPSCL1 Bit 1 PPSCL0 Bit 0 FRCCS OSCO2E OSCO2SL1 OSCO2SL0 PPSCL2
Bit 0 (FRCCS): Clock Source Select.
FRCCS 0 1 Clock Source Selected PLL Clock Source Selected IRC Clock Source
Bit 1 ~ 3 (PSR0 ~ PSR2): Prescaler for the OSCO2 clock output.
PPSCL2 0 0 0 0 1 1 1 1 PPSCL1 0 0 1 1 0 0 1 1 PPSCL0 0 1 0 1 0 1 0 1 Clock Rate 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256
36 *
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
EM77930
USB+BB Controller
Bit 4 and Bit 5 (OSCO2SL0 and OSCO1SL1): System Clock Frequency Select Control Bits
OSCO2SL0 0 0 1 1 OSCO2SL1 0 1 0 1 Output Frequency (MHz) 6 12 24 48
Bit 6 (OSCO2E):
Enable the OSCO2 output. 0: OSCO2 disabled, output low; 1: OSCO2 enabled.
Bit 7 is reserved.
7.3.10 Watchdog Timer Controller - WDTC (0x95)
Bit 7 GREEN Bit 6 Bit 5 Bit 4 WDTCE Bit 3 Bit 2 RAT2 Bit 1 RAT1 Bit 0 RAT0
Bit 0 ~ 2 (RAT0 ~ RAT2):
RAT2 0 0 0 0 1 1 1 1
Prescaler of WDT.
RAT0 0 1 0 1 0 1 0 1 Clock Rate 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256
RAT1 0 0 1 1 0 0 1 1
Bit 4 (WDTCE):
Enable the WDT Counter 0: WDT disabled 1: WDT enabled
Bits 7 (GREEN):
for power saving purposes, the system clock can be changed to external RC mode. 0: Normal Mode 1: Green Mode
Bit 3, 5 and 6 are reserved.
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
* 37
EM77930
USB+BB Controller
7.3.11 PWM Control Register - PWMCR (0x98)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 S_PWM0 Bit 1 Bit 0 -
Bit 2 (S_PWM0): Selected PWM0 output enable. 0: disable PWM output 1: enable PWM output Bits 0, 1 and 3 ~ 7 are reserved.
7.3.12 BB Interrupt Control Register - RFINTE (0x99)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CSDE TX_AEE RX_AFE TX_ EMPTYE RX_OFE LINK_ DISE LOCK_OUTE LOCK_ INE
Bit 0 (LOCK_INE):
LOCK IN interrupt enable bit.
Bit 1 (LOCK_OUTE): LOCK OUT interrupt enable bit. Bit 2 (LINK_DISE): Bit 3 (RX_OFE): LINK_DIS interrupt enable bit. The RX FIFO full interrupt enable bit.
Bit 4 (TX_EMPTYE): The TX EMPTY interrupt enable bit. Bit 5 (RX_AFE): Bit 6 (TX_AEE): Bit 7 (CSDE): The RX FIFO almost full interrupt enable bit. The TX FIFO almost empty interrupt enable bit. The carrier-sense interrupt enable bit. 0: disable function interrupt 1: enable function interrupt
7.4 USB Status, Control and Configuration Registers
These registers are function-oriented registers used by the USB to record, enable or disable the peripheral modules, interrupts, and the operation clock modes. See Section 9.5.
7.5 Code Option Code Option (ROM-0x2FFF)
Register SCLK is located on the very last bit of EM77930's 12K program ROM. These values will be fetched first to be the system initial values during power-on. SCLKC: System Clock Control Register
SCLKC 0x2FFF SCLKC 0x2FFF Bit 7 15 Bit 6 14 Bit 5 13 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SCLK0 8 -
USBCLK RFCLK1 RFCLK0 SCLK1 12 11 10 9 -
38 *
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
EM77930
USB+BB Controller
Bit 0 ~ Bit 1 (SCLK0 ~ SCLK1): System Clock Frequency Select Control Bits
SCLK1 0 0 1 1 SCLK0 0 1 0 1 System Clock (MHz) 6 12 24 48
Bits 2~3 (RFCLK0~RFCLK1): Wireless Modem Clock Frequency Select Control Bits
RFCLK1 0 0 1 1 RFCLK0 0 1 0 1 System Clock (MHz) 6 12 24 48
Bit 4 (USBCLK):
USB 48MHz PLL Clock Source Control Bit 0: Disable 48 MHz oscillation from PLL. 1: Enable 48 MHz oscillation from PLL for USB during power-on. Reserved
Bits 5 ~ 15:
SCLK [1:0] 00 00/01/10/11 01/10/11 00/01/10/11 00/01/10/11
RFCLK [1:0] 00 01/10/11 00/01/10/11 00/01/10/11 00/01/10/11
USB_ CLK 0 0 0 1 0/1
WDT_ CON.GREEN 0 0 0 0 1
SYS CLK 6 (Bypass) 6/12/24/48 12/24/48 6/12/24/48 IRC
RF CLK
USB CLK
6 (Bypass) 6 (Bypass) 12/24/48 6/12/24/48 6/12/24/48 48 48 48 -
8
Base Band (BB)
8.1 BB: Standard Interface to the RFW102 Series
8.1.1 Features
Parallel interface to RFW102 modem. Serial to Parallel conversion of RFW102 interface. Input FIFO (RX_FIFO). Output FIFO (TX_FIFO). Preamble Correlation. Packet Address Filter (Network and unique).
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
* 39
EM77930
USB+BB Controller
CRC calculation Working Frequencies: 6-24MHz Power Saving modes: Idle mode, Power-down mode Inter-RFWAVES networks Carrier-sense Discharge of the RFW-102 reference capacitor Compensate for clock drifts between the transmitting EM77930 and the receiving EM77930 up to 1000ppm. Hence, the EM77930 requires low performance crystal. Interrupt Driver - connected to the EM77930's internal interrupt and informs the EM77930 about BB events.
8.1.2 Description
RFWAVES has developed a very low cost wireless modem (RFW102) for short range, cost-sensitive applications. The modem is a physical layer element (PHY) - allowing the transmission and reception of bits from one end to the other. In an RFWAVES application, the MCU is in charge of the MAC layer protocol. In order to reduce the real-time demands of the MCU handling the MAC protocol, the BB was developed. The BB enables the MCU an easy interface to RFW102 through a parallel interface, similar to memory access. It converts the fast serial input to 8-bit words, which are much easier for an 8-bit MCU to work with and requires a lower rate oscillator. It buffers the input through a TBD bytes FIFO, enabling the MCU to access the BB more efficiently. Instead of reading one byte per interrupt, the MCU can read up to 16 bytes in each interrupt. This reduces the MCU overhead in reading incoming words, insofar as stack stuffing and pipeline emptying are concerned, in cases where each incoming byte causes an interrupt. When using the FIFO, the MCU pays the same overhead for all the FIFO bytes as it paid for only one byte without a FIFO. Having a low-cost BB with a built-in state machine that can support basic wireless communication elements would present the following advantages: Shorter development time, hence shorter time to market. Save CPU power and other resources for other applications. Offer an easy, standard integrated solution.
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EM77930
USB+BB Controller
8.1.3 I/O and Package Description
BB
7 8 RAM_ADDR [0~6] DATA [0~7] RD_n WR_n CS_n RST TX_AE RX_AF TX_EMPTY CS LOCK_IN LOCK_OUT SHDWN RF CLK Serial IO TX_RX RF_Active
MCU
RAM_ADDR [0~6] DATA [0~7] RD_n WR_n CS_n RST TX_AE RX_AF TX_EMPTY CS LOCK_IN LOCK_OUT SHDWN RF CLK
RFW-102
Data IO TX_RX RF_Active
Fig. 8-1 Parallel Interface between the MCU and RFW-102 through BB
Name
Type
Description This bus comprises of eight TRI-STATE input/output lines. The bus provides bidirectional communication between the system and the MCU. Data, control words, and status information are transferred via the DATA [0-7] data bus. When RD_n is low while the system is enabled, BB outputs one of its internal register values to DATA[0-7] according to RAM_ADDR[0-6]. When WR_n is low while the system is enabled, BB enables writing to its internal registers. The register is determined by RAM_ADDR [0-6] and the value DATA[0-7]. These four input signals determine the register to which the MCU writes to or reads from. Chip select input pin. When CS_n is low, the chip is selected; when high, the chip is disabled. This pin overrides all pins excluding RST. This enables communication between BB and the MCU. This pin functions as wake-up pin for power-down and idle modes.
DATA [0-7]
I/O
RD_n
I
WR_n
I
RAM_ADDR[0-6]
I
CS_n
I
TX_AE TX_EMPTY RX_AF CS LOCK_IN LOCK_OUT O
Interrupt driver pins. This pin goes high whenever any of the interrupt sources has an active high condition and is enabled via the IER. The purpose of this pin is to notify the MCU through its external interrupt pin that an event (such as empty TX_FIFO) has occurred. Goes low when IER register is read.
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Name
Type Chip's reset pin.
Description When this pin is set high, all registers and FIFOs are cleared to their initial values. All transceiver traffic is disabled and aborted. Reset is asynchronous to system clock. After power-up, a pulse in RST input should be applied (by POR).
RST
I
SHDWN RF_ACTIVE
I O
Shut Down BB This output pin controls the RFW102 working/shutdown mode. Its values are determined by SCR4(1). Serial input or output according to TX_RX mode. It functions as serial interface for the RFW-102 (RFWAVES modem). When SERIAL_IO is input, it is a Schmitt-trigger input. This pin controls the RFW-102 operation mode. It should be connected to RFW-102 RX_TX input pin. When RX_TX is low, RFW-102 is in receiving mode.
SERIAL_IO
I/O
RX_TX
O
When RX_TX is high, RFW-102 is in transmitting mode. In most cases RX_TX output pin is determined by SCR2(0) register. SCR3(7) and the capacitor discharge mechanism has effects on this pin.
RF_CLK
I
Clock for RF operation
8.1.4 BB Architecture
INT Interrupt Handler Address Filter
RX FIFO Parallel Interface
Receiver
Preamble Correlation
Serial Input/ Output
Address Bus Data Bus
Control & Status Registers
CRC
TX FIFO
Transmitter
Fig. 8-2 BB Block Diagram
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Product Specification (V1.0) 08.20.2007
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EM77930
USB+BB Controller
8.2 BB Description
8.2.1 Reset
A reset is achieved by holding the RST pin high for at least TBD oscillator cycles. To ensure good power-up, a reset should be given to BB after power-up.
8.2.2 Power Saving Modes
The BB is designed to work in similar working modes as a typical MCU. These modes enable the system to save power when the BB is not in use. 8.2.2.1 Power-Down Mode
The MCU can halt all activity in the BB by stopping its clock. This enables the MCU to reduce the power consumption of the BB to a minimum. All registers and FIFOs retain their values when BB is in power-down mode. BB enters power-down mode by setting the bit TBD to "1". This bit is set by MCU and cleared by BB. BB goes back to working mode by setting CS_n input pin to "0" for TBD msec. The wake-up time of the BB from power-down mode to fully operating mode is TBD msec. Since BB retains all the register values in power-down mode, special care should be given to the register values before it enters power-down. For example, the MCU should check that the BB is not in the middle of transmitting or receiving a packet. The RFACTIVE should be set low to shutdown the RFW-102, before entering power-down mode. 8.2.2.2 Idle Mode
In idle mode, the BB internally blocks the clock input. The external clock is not stopped, but it is not routed to the internal logic. By doing this, the MCU achieves substantial power savings and yet the wake-up time is still relatively short. The power consumption is not minimal since the external clock is still active. All registers and FIFOs retain their values when BB is in idle mode. BB enters idle mode by setting bit TBD to "1". This bit is set by MCU and cleared by BB. BB goes back to working mode by setting CS_n input pin to "0" for TBD sec. Since BB retains all the register values in idle mode, special care should be given to the register values before BB enters idle mode. For example, the MCU should check that the BB is not in the middle of transmitting or receiving a packet. In addition, the RFACTIVE should be set low to shutdown the RFW-102.
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8.2.3 Preamble Correlation
The transmitting BB sends the Preamble in order to synchronize the receiver to its transmission. BB transmits a fixed size Preamble of 16 bits. The received Preamble has a variable length of 16 9 bits, determined by SCR2 [5:7]. The receiver correlates the 16 9 bits from its PRE-L and PRE-H registers to the 16 9 bits in its input shift-register. If a correlation is found, then the BB receiver state machine is enabled. The purpose of the Preamble is to filter the module packets from white noise or other transmissions on the channel. NODE_ID and NET_ID filter are used to filter packets from other module networks. The Preamble is transmitted MSB to LSB (PRE-H first and then PRE-L). The value of the Preamble is determined according to PRE-L and PRE-H registers. The BB has the same Preamble when it is in transmitting mode (TX_RX=1) as when it is in receiving mode (TX_RX=0). The value of the PRE-L and PRE-H registers should be identical in the BB in all nodes in the network.
8.2.4 Refresh Bit
When receiving a valid packet, the RFWaves modem (PHY layer) has to receive a "1" symbol each time a certain period has elapsed in order to maintain its sensitivity. T he time between adjacent "1" symbols is determined by the value of the reference capacitor. This constraint is transparent to the application layer since the BB adds a "1" symbol (refresh bit) if too many "0" symbols are transmitted consecutively. On the receiver side, these additional "1" symbols (refresh bits) are removed by the BB. This feature is transparent to the application layer. The application layer has only to initialize the maximum allowed number of consecutive x"00" bytes. The BB has the flexibility to add a refresh bit every 1 to 7 bytes. This is configured by RB(0:2) bits in PPR register. The value of RB (0:2) bits in PPR register determines the overhead the refresh bit has on the throughput of the link. The refresh bit does not add substantial overhead on the bit stream, since it is only added when the number of consecutive x"00" bytes exceeds a certain value. The data that is sent is application-dependent, so the application can be adjusted in order that there will be a negligible probability of this event happening. Typical RFWaves capacitor: C=1nF Normal discharge current = 200nA Each 10mV on the capacitor represent 1dB in receiving power.
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EM77930
USB+BB Controller
200nA 1dB I = = C V 1nF 10mV 50 sec
The capacitor is charged with each received "1" symbol. The receiver is allowed to lose 1dB before a new "1" is to be received. Thus, after each 50 consecutive "0" bits in 1Mbps (50sec) a "1" symbol should be sent. In this case, setting RB [0:2] in PPR register to be 5 ("101") would be sufficient (5 bytes = 40bits). When RB (0:2) bits are set to "000" a refresh bit is added to every transmitted byte, regardless of its content. This introduces a constant overhead of 12.5%.
8.2.5 Bit Structure
The BB uses an oscillator ranging from 6 24 MHz. In order to determine the output and input bit rate, the BB must be configured to the number of clocks consisting each bit. This gives the applicator the control over the bit rate with certain restrictions. Each bit must have at least six clock cycles. The maximum bit rate is: 1Mbps The minimum bit rate is: 10Kbps (TBD) However it is recommended to work only at 1Mbps since reducing the bit rate does not change the energy of a transmitted bit. This means that reducing the bit-rate does not improve the bit error rate or the range between the transmitter and the receiver. Bit Length Register (BLR) determines the number of clock cycles per bit (bit period). BLR value is given a fixed offset of 6, since the minimum number of clock cycles in one bit is 6. Bit Rate = Oscillator / (BLR+6) The BB outputs (for the RFW-102) the bit structure shown below.
Bit "1" Structure - Even Clock Number
Bit "1" Structure - Odd Clock Number
Clock Period Bit Period
Clock Period Bit Period
Fig. 8-3 Bit Structure of the BB output to the RFW-102
In the odd number of clocks example BLR=1. In the even number of clocks example BLR=2.
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EM77930
USB+BB Controller
The number of clocks when the line is "1" is determined as follows:
BLR + 6 Number of "1" s = FLOOR - 1 2
In case of "0" bit, BB output "0" value for BLR+6 clock pulses. * FLOOR - Rounds towards zero.
8.2.6 CRC
The BB adds additional CRC information to each packet in the transmitter module, in order to enable the protocol to detect errors. The CRC is a redundant code, which is calculated and added to each packet on the transmitter side. The CRC is also calculated on the receiver side. The CRC calculation results of the receiver and the CRC field in the received packet are compared in the receiver using the CRC module in the chip. If the CRC results are equal, then the receiver knows with reasonable probability that the packet was received correctly. If the CRC results are not equal then the receiver knows with probability 1 that the packet was received incorrectly. The CRC mode is configured in the PPR (3:4) register. Both the receiving node and the transmitting node in the network have to be in the same CRC mode. The BB can apply CRC in three different ways: 16-Bit CRC - using polynomial 1+X +X +X 8-Bit CRC - using polynomial 1+X+X +X No CRC. This gives each application the flexibility to choose the adequate amount of overhead it adds to each packet and the corresponding level of protection the CRC code has. If CRC is enabled, then the BB calculates the CRC of each incoming packet. It does not put the received CRC value in the RX_FIFO. It just puts the result of its calculation in the RX_FIFO as the last byte of the packet: 0x55 - CRC received correctly. 0xAA - CRC was received incorrectly. The status bit SSR (0) stores the result of the last received packet.
2 8 2 15 16
8.2.7 RX FIFO
All received bytes are transferred to the RX_FIFO. The RX_FIFO stores the input data until the MCU reads the data from it. CRC and Preamble bytes are not transferred to the RX_FIFO.
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USB+BB Controller
The RX_FIFO is accessed just like all other read-only registers in the BB. The MCU cannot write to RX_FIFO - it can only read from it. RX_FIFO_SIZE is 16 bytes. The purpose of having an input FIFO in BB is to reduce the real-time burden from the MCU. The FIFO is used as a buffer, which theoretically enables the MCU to read the incoming data every RX_FIFO_SIZE * 8 bit/byte * 1sec = 128sec, and not every 1sec in the case of serial input, or every 8sec in the case where there is a serial to parallel converter. The actual buffer size for practical use is a bit smaller, since the MCU response time is taken into account. The MCU has three ways to learn about the RX_FIFO status: The RX FIFO Status Register (RFSR) contains the number of bytes in the RX_FIFO. BB INT pin. If configured appropriately, the INT pin will be "1" each time RX_FIFO is almost full. This invokes a MCU interrupt if the INT pin is connected to the MCU external interrupt pin. RX_FIFO Overflow Status Bit - bit RX_OF in SSR indicates when an overflow event has occurred. If a received byte is written to a full RX_FIFO, the last byte in the RX_FIFO is override and the RX_OF flag is raised. The RX_AF interrupt should invoke the MCU to read from the RX_FIFO. Using the almost full event gives the MCU 32sec (4 bytes * 8sec) to respond before it loses data, assuming a bit rate of 1Mbps. It uses most of the RX_FIFO size even if the response latency of the MCU is very short. Should the MCU not respond properly to the almost full event, and an input byte is written to the RX_FIFO when it was full, then this byte would overrun the last byte in the RX_FIFO, meaning the byte that immediately preceded it. LOCK_OUT interrupt should also trigger the MCU to read from the RX_FIFO. In case a packet has ended and the RX_AF interrupt was not invoked, the MCU should be triggered by the LOCK_OUT interrupt.
8.2.8 TX FIFO
Transmitting data is done by writing it to the TX_FIFO. The interface to the TX_FIFO is similar to all the other write-only registers in BB. The purpose of the TX_FIFO is to reduce the real-time transmission process from the MCU. The TX_FIFO enables the MCU, theoretically, to write to the TX_FIFO every 128sec and not every 8sec, as is the case with a regular 8-bit shift register. The TX_FIFO Status Register (TFSR) indicates the number of bytes in the TX_FIFO.
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The TX_FIFO can also invoke an MCU interrupt if TX_FIFO almost empty event occurs. Almost empty flag will rise when there are only four empty bytes in the TX_FIFO. It gives the MCU 32sec response time to reload the TX_FIFO in case the transmitted packet is bigger than the TX_FIFO. In case the MCU writes to a full TX_FIFO, then this byte overruns the last byte in the TX_FIFO, meaning the byte that was written just before it. Writing to a full TX_FIFO sets the TX_OF flag in SSR.
8.2.9 Interrupt Driver
The INT output pin is the summation of all interrupts source in the BB. Whenever an interrupt event has occurred and this interrupt is enabled (IER), the INT will go from low to high. The INT will remain high until the IIR register is read. The IIR register contains all the interrupt events that have occurred since the last read. It shows the event only for enabled interrupts. If an interrupt is disabled, even if the event that invoked this interrupt has occurred, the interrupt flag will be low. The IER register is used to enable/disable each of the interrupt. SCR4 (0) enables/disables all the interrupts. There are eight events in the BB that can cause the INT pin to go from low to high: 1. LOCK_IN - This interrupt indicates that the BB has started receiving a new packet. The Preamble has been identified. If the NET_ID and/or the NODE_ID are enabled, then they have been identified correctly. This event signals the beginning of an incoming packet. 2. LOCK OUT - BB has just finished receiving a packet. This means that if the BB is in fixed packet size mode, then it has finished receiving PSR bytes not including CRC bytes. If BB is not in fixed packet size mode, then it has just finished receiving a packet of size as indicated in the packet header. Although RX_STOP and setting TX_RX=1 (SCR2) terminate the receiving of the packet, they do not cause a LOCK_OUT event, since the MCU is already aware of it (the MCU initiated it). The LOCK_OUT interrupt tells the MCU when to get data out of the RX_FIFO. 3. LINK_DIS - This interrupt indicates that a "Zero counter" capacitor discharge event has occurred. If a consecutive number of zero bits (according to SCR3 (4:6)) have been received, this interrupt is set, even if zero count capacitor discharge is disabled (SCR3 (3) - EN_ZERO_DIS = '0'). The actual capacitor discharge and its interrupt are two separate registers (IER (2) for the interrupt and SCR3 (3) for the discharge). 4. RX_OF - This interrupt indicates that a byte from an incoming packet was discarded, since the RX_FIFO was already full. The receiver module tried to write a byte to a full RX_FIFO. The MCU should know that the corresponding packet is corrupted, since it is lacking at least one byte.
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EM77930
USB+BB Controller
5. TX_EMPTY - The BB has finished transmitting a packet. Meaning, the transmit shift register is empty and BB is now in RX mode (not TX mode). 6. RX_FIFO_AF - RX_FIFO is almost full. If the MCU does not want the RX_FIFO to overflow, then it should empty it. 7. TX_FIFO_AE - TX_FIFO is almost empty. If the MCU did not finish putting the transmitted packet in the TX_FIFO, then it should continue doing so now. 8. CS - CS status line has gone from "1" to "0" invokes the CS interrupt. This signals the MCU that an unidentified (NET_ID or NODE_ID or Preamble were not identified) packet has ended. If the MCU has a packet to transmit, and CS="1" then the MCU waits for this event. All these events can be masked. If an event is masked, then even if that event occurs, it does not set the INT pin to "1". The masking is done by register IER. The reason for masking is that in different applications or in different situation in the same application these events have different priorities. The MCU determines which of these events will invoke an MCU interrupt. Moreover all these events can be masked together by IE in IER register. If INT pin is set to "1", the MCU learns which event has occurred by reading IIR register. INT goes "0" when the MCU reads from IIR register.
8.2.10 Packet Size
There are two types of packet structure determined by PPR [5] (FIXED). Fixed Sized Packet - all packets have the same, fixed size. The packet size is determined in the PSR register. The packet size can be 2 255 bytes. Variable Sized Packet - the header of the incoming packet determines the packet size. One of the header bytes contains the packet size. Bits SIZE_LOC[0:1] in LCR register determines the location (offset) of the packet size inside each incoming packet header. The BB reads the packet size byte in the packet header according to LCR register. In both cases the packet size does not include the CRC addition or the Preamble.
8.2.11 NET_ID and NODE_ID Filters
NET_ID and NODE_ID are two filters in the receiver. They filter incoming packets according to their network address and node address. The address field in each incoming packet is compared to NET_ID byte and NODE_ID byte. If one of the above comparisons fails, then the packet is discarded and the MCU will not be aware of it. NET_ID and NODE_ID are both one byte. Their values are stored in NIR and BIR registers accordingly. The byte to which they are compared is set by LCR register. Each of them can be enabled or disabled independently (PPR register).
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NET_ID is targeted to be a filter on the network address. It is supposed to be common for all nodes in the network. NODE_ID is targeted to be a filter on the specific node address. It is supposed to be unique to each node in the network. The purpose of these filters is to save MCU power and to reduce its load. In a multi-node network, a node can filter all packets that are not sent to it, while in multi-network environment, a node can filter packets from other RFWaves networks. In certain network a multicast ability inside the network is required. Even if NODE_ID filter is applied, Addresses `111111XX' in NODE_ID filter are preserved for multicast transmissions. NODE_ID filter will not discard those four addresses in any case.
8.2.12 Carrier-Sense
Carrier-sense protocols are protocols in which a node (station) listens to the common channel before it starts transmitting. The node tries to identify other transmissions in order to avoid collision that might block its own transmission. In a wider perspective, a network that applies carrier-sense protocol utilizes the channel bandwidth more efficiently. A more efficient network enables lower power consumption to each node, shorter delay and higher probability of reaching the destination of each packet. The BB uses one complimentary technique in order to achieve very wide-ranging carrier-sense abilities. It has an internal implementation of RFWaves Network Carrier-Sense algorithm. This enables it to avoid collision with other RFWaves stations on its network or from other networks in the area. While the Carrier-Sense status bit in SSR (CS) tells the MCU when not to transmit, the two interrupt CS and LINK_DIS gives the MCU a flag when to transmit. LINK_DIS will be invoked whenever any transmission has ended, while CS interrupt will be invoked only when an RFWaves transmission has ended. Some applications can use some of the above mechanisms though not all of them - according to its needs. 8.2.12.1 RFWaves Carrier-Sense Algorithm Assuming our bit rate is 1Mbps. According to the described bit structure (Section 8.2.5 Bit Structure), the time difference between two rising on DATA_IO must be an integer number of 1sec. If we take into account the frequency deviation between the two BB oscillators, the time difference between two rising edges is 1sec . The depends on the frequency deviation between the two BB oscillators. The BB uses this quality in its carrier-sense algorithm. If an N (N = (CSR (0:3)*2)+2) number of "1" bits, where each is preceded by at least one "0" bit, are received with time difference of an integer number of 1sec between two consecutive "1" bits, then the CS flag in SSR equals `1'. Basically, the BB counts "0" to "1" transits on DATA_IO input, where the time difference between two transits should be an integer number (2) to 1sec. The number of consecutive "1" bits that conforms to this rule is counted in the following example (Figure 8-2) in ONE_CNT counter. ONE_CNT is incremented only if a "1" bit that comes after a "0" bit is received, where the time gap between the "1" bit and the
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EM77930
USB+BB Controller
preceding "1" bit is as mentioned above. If the time difference between two consecutive "1" bits is out of the allowed deviation, the ONE_CNT is reset. ONE_CNT is also reset if the number of consecutive "0" exceeds (CSR (4:7)*2)+2, where CSR is the last "1" bit received is counted in ZERO_CNT. ZERO_CNT is reset each time "1" bit is received. Both M and N values are determined in CSR register (CSR (7:4) and CSR (3:0) accordingly).
(0) O N E_C N T=0 ZER O _C NT=1 (1) O N E _C N T=1 ZER O _C NT=0 D A TA _IO S ignal (2) O N E _C N T=1 ZER O _C NT=1 (3) O NE _C NT=2 ZE RO _CN T=0 (4) O NE _CN T=2 ZE RO _C N T=0 (6) O NE _CN T=1 ZER O _C NT=0 (5) O N E_C N T=2 ZER O _C N T=1
1usec Search W indow
1usec
2 * 1usec S earch W indow
1usec
1usec Search W indow
Fig. 8-4 Carrier-Sense Example
In the example shown in Figure 8-2, at time (1) a new "1" bit is received after a "0" bit was received. Thus, ONE_CNT equals 1 and ZERO_CNT is reset to 0. At time (2), a zero bit is received, so the ZERO_CNT is incremented. At time (3), a "1" is received after a "0" bit that was received before it. Thus ONE_CNT is incremented and ZERO_CNT is reset. At time (4) a "1" bit is received after a "1" bit, thus, there is no change in any counter. At time (6) a "1" bit is received out of the allowed window, so ONE_CNT is reset to 1. The CSR register is used to configure the carrier-sense algorithm sensitivity. The CSR register determines the number of "1" bits that are required in order to decide that a carrier exists. The CSR also determines the number of successive "0" bits that reset the carrier-sense state machine. In SSR register, bit CS notifies whether a carrier was identified. Carrier-sense can also be used as an interrupt. When CS in SSR goes from `1' to `0' i.e. the transmission has stopped, a CS interrupt is invoked (if enabled in IER). The purpose of this interrupt is to inform the MCU that the channel is free again. If the BB identifies a packet, the carrier-sense algorithm halts. When the BB is in RX mode and the LOCK flag in SSR is "0", the CS mechanism is working. When the LOCK flag in SSR is "1", the CS mechanism is not working, since the CS flag does not add any information because a Preamble was identified already. After a Preamble was identified the CS in SSR equals `1'.
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8.2.13 Receiver Reference Capacitor Discharge
The BB implements two independent mechanisms for receiver capacitor discharge: At the end of each received packet. Zero counter. Mechanism 1 is enabled/disabled by bit EN_CAP_DISCH in SCR3. Mechanism 2 is enabled/disabled by bit EN_ZERO_DISCH in SCR3. The number of "0" bits that will cause a discharge in Mechanism 2 are determined by bits ZERO_DISCH_CNT [0:2]. For both mechanisms, the discharge time is determined by CAP_DIS_PERIOD in SCR3. Discharge is done by setting RX_TX pin to `1' for a certain time and then setting it back to `0'. (*) More detailed explanations of the reference capacitor discharge algorithms and motivations can be found in the "RFW - Capacitor Discharge.pdf" document.
8.2.14 Changing the BB Configuration
It is not recommended to change the BB configuration while it is in the middle of receiving or transmitting a packet. Thus, before writing to any of the BB control registers (such as BLR, PRE-L, PRE-H, PPR etc): Change the TX_RX mode to RX. Disable the Preamble search (SEARCH_EN in SCR2) Stop all RX receiving - RX_STOP. It is then safe to change the BB configuration.
8.2.15 Input Synchronizer
Handling asynchronous inputs to the BB.
Asynchronous Input
Synchronized Input
S R
SET
Q
S R
SET
Q
CLR
Q
CLR
Q
CLK
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EM77930
USB+BB Controller
8.3 Register Description
The registers in the BB are divided into three groups: Read-only registers which are mainly status registers. Write-only registers which are mainly control registers. Read and write registers. In case of an RST pulse, all registers are set to their default value.
8.3.1
Bit Length Register (BLR)
This register is both a read and a write register. It determines the length of the bit in terms of clock cycles. The bit length will be (BLR+6) clocks, since the minimum length of a bit is 6 clocks. Default Value: 00 (0+6=6).
8.3.2 Preamble Low Register (PRE-L)
This register is a write-only register. This register contains the 8 least significant bits of the Preamble.
Name PRE-L Bit 7 PR-7 Bit 6 PR-6 Bit 5 PR-5 Bit 4 PR-4 Bit 3 PR-3 Bit 2 PR-2 Bit 1 PR-1 Bit 0 PR-0
Default Value: 0xEB.
8.3.3 Preamble High Register (PRE-H)
This register is a write-only register. This register contains the 8 most significant bits of the Preamble.
Name PRE-H Bit 7 PR-15 Bit 6 PR-14 Bit 5 PR-13 Bit 4 PR-12 Bit 3 PR-11 Bit 2 PR-10 Bit 1 PR-9 Bit 0 PR-8
Default Value: 0xFF.
8.3.4 Packet Parameter Register (PPR)
Name PPR Bit 7 NET ID_EN Bit 6 NODE ID_EN Bit 5 FIXED Bit 4 CRC1 Bit 3 CRC0 Bit 2 RB-2 Bit 1 RB-1 Bit 0 RB-0
This is a read and a write register. It contains the control bits of the transmitted and received packet structure. Default Value: 0x3A.
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USB+BB Controller
Bits 0-2 (RB-0~RB-2): Refresh Bits These bits determine the maximum number of successive "zero" bytes allowed before an added "one" bit is stuffed to the packet by the transmitter state machine. The reason for this feature is to keep the RFW-102 reference capacitor charged.
Refresh Bit Refresh bit is added to every byte. Refresh bit is added if 1 byte equals x"00". Refresh bit is added if 2 successive bytes equal x"00". Refresh bit is added if 3 successive bytes equal x"00". Refresh bit is added if 4 successive bytes equal x"00". Refresh bit is added if 5 successive bytes equal x"00". Refresh bit is added if 6 successive bytes equal x"00". Refresh bit is added if 7 successive bytes equal x"00". Bit 2 0 0 0 0 1 1 1 1 Bit 1 0 0 1 1 0 0 1 1 Bit 0 0 1 0 1 0 1 0 1
The value of the refresh bit is determined by the value of the reference capacitor. Bits 3, 4: CRC [0:1] These bits control the CRC operation for both transmit and receive mode:
CRC No CRC CRC8 CRC8 CRC16 Bit 4 0 0 1 1 Bit 3 0 1 0 1
Bit 5:
Fixed This controls the packet mode. When high system packets are fixed size and the length is specified in the Packet Size Register (PSR). When Fixed is low, the packet size is variable. The size is specified in the header of the incoming or outgoing packets. The location of the packet size field is specified in the LCR register.
Bit 6:
NODE_ID_EN This is NODE_ID control bit. 0: Disables Node ID search 1: Enables Node ID search according to LCR, BIR
Bit 7:
NET_ID_EN This is NET_ID control bit. 0: Disables Net ID search 1: Enables Net ID search according to LCR, NIR
54 *
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
EM77930
USB+BB Controller
8.3.5
Name N/A
System Control Register 1 (SCR1)
Bit 7 N/A Bit 6 N/A Bit 5 N/A Bit 4 N/A Bit 3 N/A Bit 2 N/A Bit 1 N/A Bit 0 N/A
This byte is reserved. Default Value: 0x00.
8.3.6
Name SCR2
System Control Register 2 (SCR2)
Bit 7
PRE MASK 2
Bit 6
PRE MASK 1
Bit 5
PRE MASK 0
Bit 4 STOP RX
Bit 3
TX FIFO RESET
Bit 2
RX FIFO RESET
Bit 1 SEAR CH EN
Bit 0 TX_R X
This register is a read and a write register. This register controls the system operation modes. Bit 0: TX_RX Controls the transceiver mode: receive mode or transmit mode When TX_RX is low - BB is in receive mode (default mode). The output pin RX_TX is set to `0'. BB searches for a Preamble. If Preamble is found, it handles the process of receiving a packet. If SCR3 (7) is set, then the BB goes to RX mode and the output pin RX_TX is in TX mode. The capacitor discharge can change the output pin RX_TX to TX mode even if we are in RX mode in the BB. In this case the output pin RX_TX will be in TX for a short duration and then return to RX mode. When TX_RX is high - BB is in transmit mode. The output pin RX_TX is set to `1'. The BB handles the process of transmitting a packet according to the data in the TX_FIFO. When it finishes transmitting the packet, it automatically goes back to receive mode. Bit 1: SEARCH_EN Preamble search enable bit. When 1: Enables the search for Preamble in receive mode. When 0: Disables the search for Preamble in receive mode, (used when user configures the system while in default receive mode). This bit's default value is `0'. It must be set to `1' in order to start receiving a packet. Bit 2: RX_FIFO_RESET This bit resets the RX_FIFO address pointers when set to Logic 1. This bit is set by the MCU and is cleared automatically by the BB.
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
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Bit 3:
TX_FIFO_RESET This bit resets the TX_FIFO address pointers when set to Logic 1. This bit is set by the MCU and is cleared automatically by the BB.
Bit 4:
STOP_RX This bit stops receiving the current command, resets the RX_FIFO counters and start new searches for a preamble. This bit is set by the MCU and is cleared automatically by the BB.
Bits 5-7:
PRE_MASK [0:2]
These bits determine the mask on PRE-H in preamble correlation. Meaning, it determines the size of the Preamble in the receiver. The PRE-L is always used in the Preamble correlation. BB cuts off bit from PRE-H register, starting from the MSB.
PRE MASK 0 0 0 0 0 1 1 1 1 PRE MASK 1 0 0 1 1 0 0 1 1 PRE MASK 2 0 1 0 1 0 1 0 1 Preamble Size 16 15 14 13 12 11 10 9
Default Value: 0x60
8.3.7
Name SCR3
System Control Register 3 (SCR3)
Bit 7 LOW MODE Bit 6
ZERO DISCH CNT 2
This register is a read and a write register.
Bit 5
ZERO DISCH CNT 1
Bit 4
ZERO DISCH CNT 0
Bit 3
EN ZERO DISCH
Bit 2
CAP DIS PERIOD
Bit 1
EN CAP DISCH.
Bit 0 -
Bit 1:
EN_CAP_DISCH Enables/disables capacitor discharge mechanism after each received packet: 0: Disables discharge 1: Enables discharge This bit overrides Bit 3
56 *
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
EM77930
USB+BB Controller
Bit 2:
CAP_DIS_PERIOD Determines the capacitor discharge duration: 0: The pulse width is 36 clocks, (3 sec at 12 MHz clock). 1: The pulse width is 72 clocks, (3 sec at 24 MHz clock).
Bit 3:
EN_ZERO_DISCH Enables/disables zero counter mechanism for capacitor discharge: 0: Disables discharge 1: Enables discharge
Bits 4-6:
ZERO_DISCH_CNT [0:2]
Determine the number of zero bits that will trigger a capacitor discharge by the zero counter mechanism.
ZERO DISCH CNT 0 0 0 0 0 1 1 1 1 ZERO DISCH CNT 1 0 0 1 1 0 0 1 1 ZERO DISCH CNT 2 0 1 0 1 0 1 0 1 Number of Zeros 5 10 15 20 25 30 35 40
Bit 7:
LOW_MODE Enables or disables low power mode for RFW-102: 0: Disables low mode (normal mode) 1: Enables low mode. BB is in RX mode, while RFW-102 is in TX mode. The user has to put the BB into RX mode and to disable RX and PREAMBLE search, before enabling LOW_MODE. This transfers the RFW-102 to TX mode using RX_TX pin, while the BB is still in RX mode. RFW-102 power consumption is lower in TX mode than in RX mode. BB can not remain in TX mode, if it is not transmitting. The low mode is the combination of both of the above. Default Value: 0x01
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
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8.3.8
System Control Register 4 (SCR4)
This register is a read and a write register.
Name SCR4 Bit 7 N/A Bit 6 N/A Bit 5 N/A Bit 4 N/A Bit 3 FIFO FLAGS Bit 2 WIN CONT Bit 1 RF_ACTIVE Bit 0 IE
Bit 0:
IE This flag enables all interrupts when set to `1'. When `0', all interrupts are disabled.
Bit 1:
RF_ACTIVE This bit controls the RF_ACTIVE pin. When this bit is high, the RF Modem is active.
Bit 2:
WIN CONT This bit determines the size of the WINDOW in the Preamble search module. IF (BLR+6)>14 and WIN_CONT=1, then the preamble window size is 5.
Bit 3:
FIFO FLAGS Determines the RX_FIFO AF flag and TX_FIFO AE flag: IF FIFO FLAGS = 0 then AF = 12 and AE = 4. IF FIFO FLAGS = 1 then AF = 8 and AE = 8.
Default Value: 0x00.
8.3.9
Transmit FIFO Status Register (TFSR)
This register is a read-only register. It contains the number of bytes in the TX_FIFO. Default Value: 0x00 (TX_FIFO empty).
8.3.10 Receive FIFO Status Register (RFSR)
This register is a read-only register. It contains the number of bytes in the RX_FIFO. Default Value: 0x00 (TR_FIFO empty).
58 *
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
EM77930
USB+BB Controller
8.3.11 Location Control Register (LCR)
This is a read and a write register.
Name LCR Bit 7 Bit 6 SIZE LOC 2 Bit 5 SIZE LOC 1 Bit 4 SIZE LOC 0 Bit 3 NET LOC1 Bit 2 NET LOC 0 Bit 1 NODE LOC 1 Bit 0 NODE LOC 0
Bits 0, 1: NODE_LOC [0:1] These bits determine the location of the NODE_ID parameter in the header (the location is specified in bytes excluding preamble). The location should be fixed for all of the different kinds of packets transferred by the system. NODE_ID must never be set to be smaller than NET_ID, if both filters are enabled.
Location 2 3 4 5 NODE LOC 1 0 0 1 1 NODE LOC 0 0 1 0 1
Bits 2, 3: NET_LOC [0:1] These bits determine the location of the NET_ID parameter in the header (the location is specified in bytes excluding preamble). The location should be fixed for all of the different kinds of packets transferred by the system.
Location 1 2 3 4 NET LOC 1 0 0 1 1 NET LOC 0 0 1 0 1
Bits 4-5:
SIZE_LOC [0:2] These bits determine the location of the Packet Size parameter in the header (the location is specified in bytes excluding preamble). The location should be fixed for all of the different kinds of packets transferred by the system.
Location 2 3 4 5 6 7 8 9 Size LOC 2 0 0 0 0 1 1 1 1 Size LOC 1 0 0 1 1 0 0 1 1 Size LOC 0 0 1 0 1 0 1 0 1
Default Value: 0x00
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8.3.12 Node Identity Register (BIR)
This is a read and a write register. When the Receiver State Machine builds the incoming packet, it compares the value in the BIR register to the received data at the location specified in LCR. If the received NODE_ID and the expected NODE_ID are not equal, the packet is discarded. Four multicast NODE_ID addresses are implemented "111111XX". All packets whose 6 MSBs are "1" are not discarded. Default Value: 0x00
8.3.13 Net Identity Register (NIR)
This is a read and a write register. When the Receiver State Machine builds the incoming packet, it compares the value in the NIR to the received data at the location specified in LCR. If received NET_ID and the expected NET_ID are not equal, the packet is discarded. Default Value: 0x00
8.3.14 System Status Register (SSR)
Name
SSR
Bit 7
-
Bit 6
TX_UF
Bit 5
BIT_ERROR
Bit 4
LOCK
Bit 3
CS
Bit 2
TX EMPTY
Bit 1
LOCKED
Bit 0
CRCERROR
This register is a read-only register. It provides status information to the MCU concerning the communication line and the data transfer. Bits 1, 2, 3 can trigger the interrupt if enabled in the IER. Bits 0, 5 and 6 are set by H/W and cleared automatically after the MCU reads the register. Bits 1~4 are set and cleared by H/W Bit 0: CRC_ERROR This flag indicates a CRC Error in the packet. The CRC Block sets this flag at the end of each received packet according to the CRC calculation result. BB compares the calculated CRC and the received CRC. When these values differ, the flag goes high. The flag is cleared only after the MCU reads the SSR register. If the MCU does not read the SSR register, this flag remains "1".
60 *
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
EM77930
USB+BB Controller
Bit 1:
LOCKED This flag indicates that a packet is being received. Bit 1 is set to logic 1 whenever the system identifies a new incoming packet (triggers LOCK IN interrupt). The bit will reset to Logic 0 when the packet ends (triggers LOCK OUT interrupt) or when one of the IDs fails (NET or BYTE). This indicator is important whenever we want to switch to transmit mode because it can tell us that the line is busy and that in most cases the transmission will not succeed. The Lock triggers interrupt for every change in the bit status.
Bit 2:
TX_EMPTY This bit is the Transmitter Empty flag. When this bit is high, the system is available for loading the next packet for transmission and BB is in receive mode. When the flag is low, BB is in the middle of a packet transmission. When transmitting few successive packets, the MCU should wait to the end of a packet before it reloads the TX_FIFO with the next packet.
Bit 3:
CS Carrier Sense detection bit When this bit is high, the system has identified a structure of packet transmission in the air according to CSR. When low, no carrier has been detected. This bit is only valid in receive mode. The conditions for setting or clearing this flag are determined in the CS register. When LOCKED is high, then CS is meaningless.
Bit 4:
LOCK This signals whether a Preamble was identified or is still searching. When the flag is "0", the receiver is searching for Preamble. When the flag is "1" a Preamble was identified. If a packet was discarded for any reason, the LOCK flag goes to 1. BIT_ERROR This flag indicates that there was some error in the received package. The packet was not received according to the expected timing specifications. The packet can still pass CRC verification.
Bit 5:
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USB+BB Controller
Bit 6:
TX_UF This flag is set whenever the MCU reads a byte from an empty TX_FIFO. This flag indicates abnormal end of packet transmission. The MCU transmitter's state machine has expected to find a valid byte in the TX_FIFO according to the packet size, but it found an empty TX_FIFO. When this event occurs, the TX_EMPTY interrupt is invoked and TX_UF (underflow) flag is set to `1'. This flag is set by hardware and cleared by the MCU. It is cleared whenever the MCU reads the SSR register. Default Value: 0x04.
8.3.15 Packet Size Register (PSR)
This is a read and a write register. It contains the Packet Size in byte units. When working in fixed size packets (see Control Bit-1), the size will be fixed for all types of packets. The size in PSR excludes 2 bytes of Preamble and 2, 1 or 0 bytes of CRC. Default Value: 0x00.
8.3.16 Carrier Sense Register (CSR)
This is both a read and a write register.
Name CSR Bit 7 ZERO CNT.3 Bit 6 ZERO CNT.2 Bit 5 ZERO CNT.1 Bit 4 ZERO CNT.0 Bit 3 ONE CNT.3 Bit 2 ONE CNT.2 Bit 1 ONE CNT.1 Bit 0 ONE CNT.0
Bits 0-3:
ONE_CNT [0:3] The number of successive "1" bits that set the carrier sense high.
Bits 4-7:
ZERO_CNT [0:3] The number of successive "0" bits that reset the carrier sense (CS='0'). Default Value: 0x44
62 *
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
EM77930
USB+BB Controller
8.4 Interrupt Registers
8.4.1
Name
IER
Interrupt Enable Register (IER)
Bit 7
CS
This register is a write and a read register.
Bit 6
TX_AE
Bit 5
RX AF
Bit 4
TX EMPTY
Bit 3
RX_OF
Bit 2
LINK_D IS
Bit 1
LOCK OUT
Bit 0
LOCK IN
Default Value: 0x00. For all flags in this register, 0: Disable 1: Enable Bit 0: LOCK_IN This flag enables/disables the LOCK IN interrupt. PREABLE + NODE_ID + NET_ID identified correctly triggers LOCK IN interrupt. Bit 1: LOCK_OUT This flag enables/disables the LOCK OUT interrupt. End of received packet triggers LOCK_OUT interrupt. Bit 2: LINK_DIS This flag enables/disables the LINK_DIS interrupt. The zero counter capacitor discharge triggers the LINK_DIS interrupt. Bit 3: RX_OF This flag enables/disables the RX_OF interrupt. End of received packet triggers RX_OF interrupt. Bit 4: TX_EMPTY This flag enables/disables the TX_EMPTY (Transmitter Empty) interrupt. TX_EMPTY interrupt tell the MCU that the transmitter has just finished transmitting a packet. BB goes to RX mode after finishing the transmission of a packet. Bit 5: RX_AF This flag enables/disables the RX_AF interrupt. The RX_AF interrupt is triggered when RX_FIFO AF flag goes from `0' to `1'. Bit 6: TX_AE This flag enables/disables the TX_AE interrupt. The TX_AE interrupt is triggered when TX_FIFO AE flag goes from `0' to `1'. Bit 7: CS This flag enables/disables the CS interrupt. CS flag in SSR negative edge triggers CS interrupt.
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
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8.4.2
Name IIR
Interrupt Identification Register (IIR)
Bit 7 CS Bit 6
TXAE
Bit 5
RX AF
Bit 4
TXEMPTY
Bit 3
RX_OF
Bit 2
LINK_DIS
Bit 1
LOCKOUT
Bit 0
LOCKIN
This is a read only register. When the MCU accesses the IIR, all interrupts freeze. While the MCU access is occurring, the system records the changes in the interrupts but waits until the MCU access is complete before updating the register. A flag is active only when the matching interrupt enable bit is set, and does not depend on the IE bit value. The flags are set by H/W and cleared after the MCU reads the register. Bit 0: This bit reflects the LOCK IN flag interrupt when enabled by IER. This bit reflects the LOCK IN flag interrupt when enabled by IER. LOCK_IN interrupt is invoke whenever a PREAMBLE+NET_ID+NODE_ID where recognized. If NET_ID is disabled, then a received PREAMBLE+ NODE_ID invokes the interrupt. If NODE_ID is disabled, then a received PREAMBLE+ NET_ID invokes the interrupt. If NET_ID and NODE_ID are disabled, then a received PREAMBLE invokes the interrupt. Bit 1: This bit reflects the LOCK OUT flag interrupt when enabled by IER. This bit reflects the LOCK OUT flag interrupt when enabled by IER. LOCK_OUT interrupt is invoked whenever RFW-D100 has finished receiving a packet. The end of the packet is determined according to the packet size. Bit 2: This bit reflects the LINK_DIS flag interrupt when enabled by IER. This interrupt is invoked by the zero counter capacitor discharge mechanism. Bit 3: Bit 4: Bit 5: Bit 6: Bit 7: This bit reflects the RX_OF flag interrupt when enabled by IER. This bit reflects the TX EMPTY flag interrupt when enabled by IER. This bit reflects the RX FIFO AF flag interrupt when enabled by IER. This bit reflects the TX FIFO AE flag interrupt when enabled by IER. CS - when CS flag goes from "1" to "0" an interrupt is invoked.
64 *
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
EM77930
USB+BB Controller
8.5 List of BB Register Mapping
Register Address 0 (00000) 1 (00001) 2 (00010) 3 (00011) 4 (00100) 5 (00101) 6 (00110) 7 (00111) 8 (01000) 9 (01001) 10 (01010) 11 (01011) 12 (01100) 13 (01101) 14 (01110) 15 (01111) 16 (10000) 17 (10001) 18 (10010) 19 (10011) 20 (10100) --------Write TX_FIFO PRE_L PRE_H FRC_L FRC_H SCR1 SCR2 SCR3 SCR4 LCR BIR NIR PSR PPR BLR CSR IER IIR SSR TFR RFR --------0x04 0x00 0x00 Read RX_FIFO Default Values --0xFF 0xFF 0xFF 0xFF 0x00 0x60 0x01 0x00 0x00 0x00 0x00 0x00 0x3A 0x00 0x44 0x00 ---
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8.6
MCU BB Control Registers
8.6.1 Control Registers List
Register R2D indicates BB indirect RAM address. Register R2E indicates BB indirect RAM data. Register R2F indicates BB RAM access control.
Bit 5 Bit 4 Bit 3 Bit 2 RRST Bit 1 RFRD Bit 0 RFWR
RFAAR (0x2D): RFDB (0x2E): RFACR (0x2F):
Bit 7 Bit 6 -
RFINTF (0x30): BB interrupt flags
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CSDF TX_AEF RX_AFF TX_ EMPTYF RX_OFF LINK_ DISF LOCK_OUTF LOCK_ INF
RFINTE (0x99): BB interrupt enable
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CSDE TX_AEE RX_AFE TX_ EMPTYE RX_OFE LINK_ DISE LOCK_OUTE LOCK_ INE
PRIE (0x80): Peripherals enable control
Bit 7 Bit 6 USBE Bit 5 BBE Bit 4 Bit 3 Bit 2 PWM0E Bit 1 TCCE Bit 0 FRCE
66 *
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
EM77930
USB+BB Controller
8.6.2
ORG BC
BB Control Example
0X0060 RFINTF, TX_EMPTYF // TX_EMPTY INT address // RF data send out, clear INT flag.
RETI ORG START: BS NOP BC BS MOV MOV ENI RF_TX_INITIAL: WRITE WRITE WRITE #SCR2, #8 #BLR, #10 #PPR, #33 // Reset TX_FIFO, RX mode. // Set bit rate. // Set package size to be fixed. // Refresh bit mode 1. CRC disabled WRITE WRITE WRITE #PSR, #6 #PRE_H, #0xDC #PRE_L, #0xA7 // Set package size to 6. // Set preamble High byte value. // Set preamble Low byte value. RF_SEND_DATA: WRITE WRITE WRITE WRITE WRITE WRITE READ WRITE WRITE WRITE #TX_FIFO, #0x01 #TX_FIFO, #0x02 #TX_FIFO, #0x03 #TX_FIFO, #0x04 #TX_FIFO, #0x05 #TX_FIFO, #0x06 #TFR, 0x60 #IER, #16 #SCR4, #0x03 #SCR2, #1 // Write last byte of package to TX_FIFO. // Read TFR register data // enable TX_EMPTY INT // enable all INT. // move from RX to TX mode.
* 67
0X0100 RFACR, RRST RFACR, RRST PRIE, BBE A, #0x10 RFINTE, A // BB power enable. // BB INT.TX_EMPTY enable. // enable all INT. // BB reset.
// Write first byte of package to TX_FIFO.
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
EM77930
USB+BB Controller
LOOP: JMP LOOP // BB register write SUB
WRITE_DATA_TO_RF: BC NOP NOP BS RET RFACR, RFWR RFACR, RFWR
READ_DATA_FROM_RF: NOP NOP NOP NOP BC NOP NOP NOP NOP NOP MOV NOP NOP NOP BS RET RFACR, RFRD RFACR, RFRD
// BB register read SUB
// Note the access time A, RFDB
; =============================================== WRITE MACRO MOV MOV MOV MOV CALL ENDM ; =============================================== READ MACRO #CON, REG // BB register read MACRO MOV MOV CALL MOV ENDM
68 * Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
#CON1, #CON2 A, #CON2 RFDB, A A, #CON1 RFAAR, A WRITE_DATA_TO_RF
// BB register write MACRO
A, #CON RFAAR, A READ_DATA_FROM_RF REG, A
EM77930
USB+BB Controller
9
Universal Serial Bus (USB)
9.1 Block Diagram
rst_n usbclk usben
speed suspend tx_dp tx_dm tx_oe_n rx_dp rx_dm rxd
mcu_clk usbint rden 10
Transceiver
USB Device
rdadr 8 ubus wren wradr dbus 8 8 8
MCU
Fig. 9-1 USB Function Block Diagram of the EM77930
9.2 USB FIFO Allocation
End Point Number 0 1 2 3 End Point Type Control Interrupt / Bulk / Isochronous Interrupt / Bulk / Isochronous Interrupt / Bulk / Isochronous FIFO Size 64 byte IN 64 byte OUT 64 byte IN / OUT 64 byte IN / OUT 64 byte IN / OUT
Product Specification (V1.0) 08.20.2007
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9.3 Pin Description
Pin usben usbclk rst_n I/O I I I USB module enable 48MHz clock for USB device Reset Active low hardware reset signal to the USB. Speed speed O USB device speed 1: full speed device 0: low speed device Transceiver suspend suspend O Enable /disable transceiver when port suspend 1: Disable transceiver 0: Enable transceiver tx_dp tx_dm tx_oe_n rx_dp rx_dm rxd mcuclk usbint[9:0] rden O O O I I I I O I USB output data puls USB output data minus USB data output enable USB input data plus USB input data minus USB Input data Clock signal from mcu Interrrup output Active high signals generated by the USB to the MCU. Read enable The signal is asserted high for a read operation. Read address bus rdadr[7:0] I Read address generated by MCU for the USB register. selection. Data output Data bus output to MCU Write enable The signal is asserted high for a write operation Write address bus wradr[7:0] I Write address generated by MCU for the USB register. selection Data input Data bus input to MCU Description
ubus[7:0] wren
O I
dbus[7:0]
I
70 *
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
EM77930
USB+BB Controller
9.4 Timing Diagram of MCU Interface
tcycle
clk
trs trh
rden
tras trah
rdadr
trdv
ubus
tws twh
wren
twas twah
wradr
twds twdh
dbus
Fig. 9-2 MCU Interface Timing Diagram
Symbol tcycle trs trh tras trah trdv tws twh twas twah twds twdh
Parameter MCU clock cycle time Read enable setup time Read enable hold time Read address setup time Read address hold time Read data valid time Write enable setup time Write enable hold time Write address setup time Write address hold time Write data setup time Write data hold time
Min 20ns 3ns 0.1ns 3ns 0.1ns - 3ns 0.1ns 3ns 0.1ns 3ns 0.1ns
Max - - - - - 5ns - - - - - -
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9.5 USB Device Register Summary
Register
GCNTR
ADDR
0x1CD
Reset
-
Bit 7
SPD P
Bit 6
- -
Bit 5
- - EPEN EPEN EPEN INT3 INT3E - - - ADDR5 - STALLSTS STALLSTS STALLSTS1 STALLSTS2 STALLSTS3 EP0RXCT5
Bit 4
- - - - - INT2 INT2E - - - ADDR4 - ACKSTS ACKSTS ACKSTS1 ACKSTS2 ACKSTS3 EP0RXCT4
Bit 3
RESUME P/H - - - INT1 INT1E - - - ADDR3 - DTOGERR - DTOGERR1 DTOGERR2 DTOGERR3 EP0RXCT3 EP0TXCT3 EP1CT3 EP2CT3 EP3CT3 DATA 3 DATA 3 DATA 3 DATA 3 DATA 3 - - FNLR3 -
Bit 2
SUSPEND P/H EPDIR EPDIR EPDIR INT0IN INT0INE RUEINT P/H RUEINTE ADDR2
Bit 1
PLUG P EPTYPE1 EPTYPE1 EPTYPE1 INT0TX INT0TXE IDLEINT P/H IDLEINTE ADDR1
Bit 0
URST P/H EPTYPE0 EPTYPE0 EPTYPE0 INT0RX INT0RXE RSTINT P RSTINTE ADDR0 OUT RXEN TXEN RXTXEN1 RXTXEN2 RXTXEN3 EP0RXCT0 EP0TXCT0 EPCT0 EPCT0 EPCT0 DATA 0 DATA 0 DATA 0 DATA 0 DATA 0 - - FNLR0 FNHR8
EP1CNTR EP2CNTR EP3CNTR EPINTR EPINTE
0x1CE 0x1CF 0x1D0 0x1D1 0x1D2
P/H/S P/H/S P/H/S P P
- - - - - -
- - - - - - - - ADDR6 - ERRSTS ERRSTS ERRSTS1 ERRSTS2 ERRSTS3 EP0RXCT6
STAINTR
0x1D3
P
- - - - CDTOG CDTOG CDTOG1 CDTOG2 CDTOG3 - - - - - DATA7 DATA7 DATA7 DATA7 DATA7 - - FNLR7 -
STAINTE FAR EP0RXTR EP0RXCSR EP0TXCSR EP1CSR EP2CSR EP3CSR EP0RXCTR EP0TXCTR EP1CTR EP2CTR EP3CTR EP0RXDAR EP0TXDAR EP1DAR EP2DAR EP3DAR HINTR HINTE FNLR FNHR
0x1D4 0x1D5 0x1D6 0x1D7 0x1D8 0x1D9 0x1DA 0x1DB 0x1DC 0x1DD 0x1DE 0x1DF 0x1E0 0x1E1 0x1E2 0x1E3 0x1E4 0x1E5 0x1E7 0x1E8 0x1FE 0x1FF
P P P P/H/S P/H/S P/H/S P/H/S P/H/S X H/S H/S H/S H/S X X X X X X X X X
SETUPOW SETUP DTOG DTOG DTOG1 DTOG2 DTOG3 EP0RXCT2 EP0TXCT2 EPCT2 EPCT2 EPCT2 DATA 2 DATA 2 DATA 2 DATA 2 DATA 2 - - FNLR2 FNHR10 SESTALL SESTALL SESTALL1 SESTALL2 SESTALL3 EP0RXCT1 EP0TXCT1 EPCT1 EPCT1 EPCT1 DATA 1 DATA 1 DATA 1 DATA 1 DATA 1 - - FNLR1 FNHR9
EP0TXCT6 EP0TXCT5 EP0TXCT4 EP1CT6 EP2CT6 EP3CT6 DATA 6 DATA 6 DATA 6 DATA 6 DATA 6 SOFINT SOFINTE FNLR6 - EP1CT5 EP2CT5 EP3CT5 DATA 5 DATA 5 DATA 5 DATA 5 DATA 5 - - FNLR5 - EP1CT4 EP2CT4 EP3CT4 DATA 4 DATA 4 DATA 4 DATA 4 DATA 4 - - FNLR4 -
Legend: "P" = Power-on reset
"H" = Hardware reset
"S" = Software reset
72 *
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
EM77930
USB+BB Controller
9.5.1
Bit
General Control Register (GCNTR)
Field HW SW DF Description Software Reset S/W sets this bit and will reset the whole USB compound device. All registers return to their default value and the USB compound device will be in the default state. H/W will clear this bit after the reset is completed. Connect USB device When set to 1 by S/W, 1 will be driven to the connecting pin, thus the pull-high resistance is connected to the USB bus, and the USB compound device is connected to the USB bus.
0
RESET
R/W0C
R/W
0
1
PLUG
R
R/W
0
When cleared to 0 by S/W, 0 will be driven to the connecting pin, thus the pull-high resistance is not connected to the USB bus, and the USB compound device is not connected to the USB bus. This bit will be reset by SW reset and USB reset. Suspend State Enable Set by SW to force the USB device to enter suspend state. SW is allowed to set this bit if the USB bus has been in the idle state for more than 3ms. The USB device will leave the suspend state if the SW clears this bit or the resume bit is set. This bit will be cleared by HW if the resume bit is set. This bit will be reset by SW reset and USB reset. Send Resume to USB Bus When set to 1, the USB device will send resume signal to the USB bus after the USB bus has been in the idle state for more than 5ms. The resume signal will be driven for 5ms. HW will clear this bit after completing resume sending.
2
SUSPEND
R/W0C
R/W
0
3
RESUME
R/W0C
R/W
0
6-4 7
Reserved USB function speed setting SPD R R/W 1 0: Low-speed device 1: Full-speed device
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
* 73
EM77930
USB+BB Controller
9.5.2
Endpoint n Control Register (EP1/2/3CNTR)
Endpoint 1 Control Register (EP1CNTR) Endpoint 2 Control Register (EP2CNTR) Endpoint 3 Control Register (EP3CNTR)
Bit Field HW SW DF Description Endpoint Type. These bits program the type of endpoint. Bit 1 Bit 0 1-0 EPTYPE R R/W 3 0 0 1 1 2 4-3 5 7-6 EPDIR Reserved Endpoint Enable/Disable EPEN Reserved R R/W 0 0=Disable endpoint 1=Enable endpoint R R/W 1 0=OUT 1=IN 0 1 0 1 Type Un-used Isochronous Bulk Interrupt
Endpoint Direction
9.5.3
Bit
Endpoint Interrupt Event Register (EPINTR)
Field HW SW DF Description EP0 USB RX Event Set by HW when either SETUP transaction ends with ACK or OUT transaction ends with ACK or STALL. It is also set when SETUPOW (EP0RXTR Register) bit is set. Needs to check EP0RXCSR Register for details. When SW clears all the OUT, SETUP and SETUPOW bits in the EP0RXTR Register, this bit will be cleared automatically. EP0 USB TX Event Set by HW when IN transaction ends with ACK or STALL.
0
INT0RX
R/W
R
0
1
INT0TX
R/W R/W0C
0
When S/W writes a 0, it will clear this bit, when 1 is written, no change occurs. H/W write operation has a higher priority if H/W write and S/W write occur at the same time.
74 *
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
EM77930
USB+BB Controller
Bit
Field
HW
SW
DF
Description EP0 USB IN Token Event Set by HW when a valid IN token is received. When S/W writes a 0, it will clear this bit, when 1 is written, no change occurs. H/W write operation has a higher priority if H/W write and S/W write occur at the same time. EP1 Interrupt Set by HW when IN transaction (Interrupt IN / Bulk IN / Isochronous IN) ends with ACK or STALL or OUT transaction (Bulk OUT / Isochronous OUT) ends with ACK or STALL. IN or OUT transaction is determined by Endpoint Type. When S/W writes a 0, it will clear this bit, when 1 is written, no change occurs. H/W write operation has a higher priority if H/W write and S/W write occur at the same time. EP2 Interrupt Set by HW when IN transaction (Interrupt IN / Bulk IN / Isochronous IN) ends with ACK or STALL or OUT transaction (Bulk OUT / Isochronous OUT) ends with ACK or STALL. IN or OUT transaction is determined by Endpoint Type. When S/W writes a 0, it will clear this bit, when 1 is written, no change occurs. H/W write operation has a higher priority if H/W write and S/W write occur at the same time. EP3 Interrupt Set by HW when IN transaction (Interrupt IN / Bulk IN / Isochronous IN) ends with ACK or STALL or OUT transaction (Bulk OUT / Isochronous OUT) ends with ACK or STALL. IN or OUT transaction is determined by Endpoint Type. When S/W writes a 0, it will clear this bit, when 1 is written, no change occurs. H/W write operation has a higher priority if H/W write and S/W write occur at the same time.
2
INT0IN
R/W R/W0C
0
3
INT1
R/W R/W0C
0
4
INT2
R/W R/W0C
0
5
INT3
R/W R/W0C
0
6 7
Reserved Reserved
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
* 75
EM77930
USB+BB Controller
9.5.4
Bit 0 1 2 3 4 5 6 7
Endpoint Interrupt Event Enable Register (EPINTE)
Field INT0RXE INT0TXE INT0INE INT1E INT2E INT3E Reserved Reserved HW R R R R R R SW R/W R/W R/W R/W R/W R/W DF 0 0 0 0 0 0 Description EP0 USB RX Event Enable EP0 USB TX Event Enable EP0 USB IN Token Event Enable EP1 interrupt Enable EP2 interrupt Enable EP3 interrupt Enable
9.5.5
Bit
State Interrupt Event Register (STAINTR)
Field HW SW DF Description USB Bus Reset Event Detect Set by HW when reset signal is detected on the USB bus. After a USB bus reset, all registers return to their default value and the USB device will be in the default state. When S/W writes a 0, it will clear this bit, when 1 is written, no change occurs. H/W write operation has a higher priority if H/W write and S/W write occur at the same time. USB Bus Suspend Detect Set by HW when the USB bus is idle every 3ms. When S/W writes a 0, it will clear this bit, when 1 is written, no change occurs. H/W write operation has a higher priority if H/W write and S/W write occur at the same time. USB Bus Resume Detect Set by HW when resume signal is detected. When S/W writes a 0, it will clear this bit, when 1 is written, no change occurs. H/W write operation has a higher priority if H/W write and S/W write occur at the same time.
0
RSTINT
R/W
R/W0C
0
1
IDLEINT
R/W
R/W0C
0
2
RUEINT
R/W
R/W0C
0
7-3
Reserved
9.5.6
Bit 0 1 2 7-3 76 *
State Interrupt Event Enable Register (STAINTE)
Field RSTINTE IDLEINTE RUEINTE Reserved Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
HW R R R
SW R/W R/W R/W
DF 0 0 0
Description Enable USB Bus Reset Event Detect Enable USB Bus Suspend 3ms Detect Enable USB Bus Resume Detect
EM77930
USB+BB Controller
9.5.7
Bit 6-0 7
Function Address Register (FAR)
Field ADDR Reserved HW R SW R/W DF 0 Description USB Device Address
9.5.8
Bit
Endpoint 0 RX Token Register (EP0RXTR)
Field HW SW DF Description RX OUT Token Set by HW to indicate OUT token is received and transaction ends with ACK or STALL. When S/W writes a 0, it will clear this bit, when 1 is written, no change occurs. RX SETUP Token Set by HW to indicate SETUP token is received and transaction ends with ACK. When S/W writes a 0, it will clear this bit, when 1 is written, no change occurs. SETUP Overwrite Set by HW to indicate SETUP token is received when RX FIFO is not empty (regardless whether it is ended with error or ACK). When S/W writes a 0, it will clear this bit, when 1 is written, no change occurs.
0
OUT
R/W R/W0C
0
1
SETUP
R/W R/W0C
0
2
SETUPOW
R/W R/W0C
0
7-3
Reserved
9.5.9
Bit
Endpoint 0 RX Command/Status Register (EP0RXCSR)
Field HW SW DF Description RX Enable Set by SW to enable rx USB data. USB data will be written to FIFO and ACK will be returned if the bit "SESTALL" is not set. Clear by HW to indicate transaction ends with ACK or STALL. If this bit is 0,USB data will be discarded and NAK will be returned. SETUP packets will be written to FIFO even this bit is not set and ACK will be returned always. This register will be reset by USB reset or SW reset. Send STALL If set, STALL will be returned to the OUT transaction. SW is allowed to set or clear this bit. HW clears this bit when SETUP transaction ends with ACK. HW sets this bit when STALL is returned to any EP0 transaction. * 77
0
RXEN
R/W0C R/W
1
1
SESTALL
R/W
R/W
1
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
EM77930
USB+BB Controller
Bit 2
Field DTOG
HW R/W
SW R
DF Data Toggle Bit 0
Description Updated by HW to indicate the data toggle bit for current USB transaction. Data Toggle Error Set by HW to indicate toggle error occurs. Cleared when SW writes a 0 to clear the EP0 RX event interrupt status. ACK Status Set by HW when a transaction is completed with ACK handshake. This bit will be updated automatically at the next valid transaction (ends with ACK or STALL). STALL Status Set by HW when a transaction is completed with STALL handshake. This bit will be updated automatically at the next valid transaction (ends with ACK or STALL). Error Status Set by HW to indicate either USB PID error, CRC error, bit stuffing error or no data phase from USB host occur. This bit will be updated automatically at the next valid transaction (ends with ACK or STALL) or when SETUPOW (EP0RXTR Register) is set. Clear Endpoint Toggle. When SW writes a 1 to this bit, it will clear the DTOG bit which is in the same register.
3
DTOGERR
R/W
R
0
4
ACKSTS
R/W
R
0
5
STALLSTS
R/W
R
0
6
ERRSTS
R/W
R
0
7
CDTOG
R/W0C
W
0
9.5.10 Endpoint 0 TX Command/Status Register (EP0TXCSR)
Bit Field HW SW DF TX Enable Set by SW to enable Tx USB data. USB data Is ready in the FIFO and will be sent to USB bus if the bit "SESTALL" is not set. SW should write data then byte count the enabled Tx. Cleared by HW in two cases: Indicate IN transaction ends with ACK or STALL.. After SETUP transaction ends with ACK. This register will be reset by USB reset or SW reset. Send STALL If set, STALL will be returned to the IN transaction. SW is allowed to set or clear this bit. HW clears this bit when SETUP transaction ends with ACK. HW sets this bit when STALL is returned to any EP0 transaction. Description
0
TXEN
R/W0C R/W
0
1
SESTALL
R/W
R/W
1
78 *
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
EM77930
USB+BB Controller
Bit 2 3
Field DTOG Reserved
HW R/W
SW R
DF Data Toggle Bit 1
Description Updated by HW to indicate the data toggle bit for current USB transaction.
ACK Status 4 ACKSTS R/W R 0 Set by HW when a transaction is completed with ACK handshake. This bit will be updated automatically at the next valid transaction (ends with ACK or STALL). STALL Status 5 STALLSTS R/W R 0 Set by HW when a transaction is completed with STALL handshake. This bit will be updated automatically at the next valid transaction (ends with ACK or STALL). Error Status 6 ERRSTS R/W R 0 Set by HW to indicate either USB PID error, CRC error, bit stuffing error or no data phase from USB host occur. This bit will be updated automatically at the next valid transaction (ends with ACK or STALL) or when SETUPOW (EP0RXTR Register) is set. Clear endpoint Toggle. 7 CDTOG R/W0C W 0 When SW writes a 1 to this bit, it will clear the DTOG bit which is in the same register.
9.5.11 Endpoint 0 RX Count Register (EP0RXCTR)
Bit Field HW SW DF Description RX Byte Count When receive enable is set to 1, this field specifies the receive byte counts in the receive FIFO. This register will be reset by USB reset or SW reset.
0-6
EP0RXCT
R/W
R
0
7
Reserved
9.5.12 Endpoint 0 TX Count Register (EP0TXCTR)
Bit Field HW SW DF Description TX Byte Count When transmit enable is set to 1, this field specifies the transmit byte counts in the transmit FIFO. HW always accesses the FIFO from address0. This register will be reset by USB reset or SW reset.
0-6
EP0TXCT
R
R/W
0
7
Reserved
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
* 79
EM77930
USB+BB Controller
9.5.13 Endpoint 0 RX Data Register (EP0RXDAR)
Bit 0-7 Field DATA HW R/W SW R DF 0 RX Data Receive FIFO data will be read by SW through read this register. Description
9.5.14 Endpoint 0 TX Data Register (EP0TXDAR)
Bit 0-7 Field DATA HW R SW W DF 0 TX Data SW writes data to this register will be written to transmit FIFO. Description
9.5.15 Endpoint n Command/Status Register (EPnCSR)
Endpoint 1 command/status Register (EP1CSR) Endpoint 2 command/status Register (EP2CSR) Endpoint 3 command/status Register (EP3CSR)
Bit Field HW SW DF Description RX Enable (Interrupt Out / Bulk Out / Isochronous Out) Set by SW to enable rx USB data. USB data will be written to FIFO and ACK will be returned if the bit "SESTALL" is not set. Cleared by HW to indicate transaction ends with ACK or STALL. If this bit is 0, the USB data will be discarded and NAK will be returned. TX Enable (Interrupt In/Bulk In /Isochronous IN) Set by SW to enable Tx USB data. USB data is ready in the FIFO and will be sent to the USB bus if the bit "SESTALL" is not set. SW should write data then byte count the enabled Tx. Cleared by HW when the IN transaction ends with ACK or STALL. If the transaction ends with ACK, the following USB transaction will be returned with NAK if the bit "SESTALL" is not set. The register will be reset by USB reset or SW reset. Send STALL If set, STALL will be returned for the transaction. SW is allowed to set or clear this bit. Reserved (Isochronous IN or Isochronous OUT) Data Toggle Bit (Interrupt IN / Interrupt OUT / Bulk IN / Bulk OUT) Updated by HW to indicate the data toggle bit for current USB transaction. Reserved (Isochronous IN or Isochronous OUT)
0
RXTXEN
R/W0C R/W
0
1
SESTALL
R/W
R/W
1
2
DTOG
R/W
R
0
80 *
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
EM77930
USB+BB Controller
Bit
Field
HW
SW
DF
Description Data Toggle Error (Interrupt OUT / Bulk OUT) Reserved (Interrupt In / Bulk In / Isochronous IN / Isochronous OUT) Set by HW to indicate toggle error occurs. Cleared when SW writes a 0 to clear the EPn OUT event interrupt status. ACK Status Set by HW when a transaction is completed with ACK handshake. This bit will be updated automatically at the next valid transaction (ends with ACK or STALL). STALL Status Set by HW when a transaction is completed with STALL handshake. This bit will be updated automatically at the next valid transaction (ends with ACK or STALL). Error Status Set by HW to indicate either USB PID error, CRC error, bit stuffing error, time out without handshake response from USB host (for IN transaction) or no data phase from USB host occur (OUT transaction). This bit will be updated automatically at the next valid transaction (ends with ACK or STALL). Clear endpoint Toggle. When SW writes 1 to this bit, it will clear the DTOG bit which is in the same register. Reserved (Isochronous IN or Isochronous OUT)
3
DTOGERR
R/W
R
0
4
ACKSTS
R/W
R
0
5
STALLSTS
R/W
R
0
6
ERRSTS
R/W
R
0
7
CDTOG
R/W0C
W
0
The following table lists the meaning of the Endpoint n command/status Register (EPnCSR) for different Endpoint-Type.
Bit Interrupt IN Interrupt OUT 0 1 2 3 4 5 6 7 RXTXEN SESTALL DTOG Reserved ACKSTS STALLSTS ERRSTS CDTOG RXTXEN SESTALL DTOG DTOGERR ACKSTS STALLSTS ERRSTS CDTOG Bulk IN RXTXEN (TX Enable) SESTALL DTOG Reserved ACKSTS STALLSTS ERRSTS CDTOG Bulk OUT RXTXEN (RX Enable) SESTALL DTOG DTOGERR ACKSTS STALLSTS ERRSTS CDTOG Isochronous Isochronous IN OUT RXTXEN (TX Enable) Reserved Reserved Reserved ACKSTS STALLSTS ERRSTS Reserved RXTXEN (RX Enable) Reserved Reserved Reserved ACKSTS STALLSTS ERRSTS Reserved
(TX Enable) (RX Enable)
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
* 81
EM77930
USB+BB Controller
9.5.16 Endpoint n Count Register (EPnCTR)
Endpoint 1 count Register (EP1CTR) Endpoint 2 count Register (EP2CTR) Endpoint 3 count Register (EP3CTR)
Bit Field HW SW DF Description RX Byte Count (Bulk Out / Isochronous Out) When receive enable is set to 1, this field specifies the receive byte counts in the receive FIFO. TX Byte Count (Interrupt In / Bulk In / Isochronous In) When transmit enable is set to 1, this field specifies the transmit byte counts in the transmit FIFO. HW always accesses the FIFO from Address 0. This register will be reset by USB reset or SW reset.
0-7
EPnCT
R/W
R/W
0
7
Reserved
9.5.17 Endpoint n Data Register (EPnDAR)
Endpoint 1 Data Register (EP1DAR) Endpoint 2 Data Register (EP2DAR) Endpoint 3 Data Register (EP3DAR)
Bit Field HW SW DF Description RX Data (Bulk Out / Isochronous Out) Receive FIFO data will be read by SW through reading this register. TX Data (Interrupt In / Bulk In / Isochronous In) SW writes data to this register will be written to transmit FIFO.
0-7
DATA
R/W
R or W
0
9.5.18 USB Device SOF Event Register (HINTR)
Bit 0-5 6 7 Field Reserved SOFINT Reserved R/W R/W0C 0 Start of frame interrupt. Asserted after the receipt of a valid SOF. HW SW DF Description
9.5.19 USB Device SOF Event Enable Register (HINTE)
Bit 0-5 6 7 Field Reserved SOFINTE Reserved R R/W 0 SOF Interrupt Event Enable. HW SW DF Description
9.5.20 Frame Number Low-Byte Register (FNLR)
Bit 0-7 Field FNLR HW R/W SW R DF 0 Description Bits 0~7 of Frame Number (11 bits)
9.5.21 Frame Number High-Byte Register (FNHR)
Bit 0-2 3-7 82 * Field FNHR Reserved HW R/W SW R DF 0 Description Bits 8~10 of Frame Number (11 bits)
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
EM77930
USB+BB Controller
10 Pulse Width Modulation (PWM)
10.1 Overview
The EM77930 has one PWM output with 16-bit resolution. Fig. 10-1 shows the functional block diagram. A PWM output has a period and a duty cycle, and it keeps the output high. The baud rate of the PWM is the inverse of the period. Fig. 10-2 depicts the relationships between a period and a duty cycle.
PWM0IF
DT0H
DT0L
DL0H Set as compare match
DL0L
PWM0E S_PWM0
Duty Compare Circuit
PWM0IE Data Bus
PWM0
Q
R TMR0HB TMR0LB
S
Set as compare match
Period Compare Circuit
MUX
PRD0H
PRD0L
PWM0E Fosc/2
Fig. 10-1 PWM Functional Block Diagram
Period
Period
Period
Duty DUTY = TMR
Duty PRD= TMR
Duty
Fig. -2 PWM Output Timing Diagram Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
* 83
EM77930
USB+BB Controller
10.2 PWM Control Registers
As the PWM mode is defined, the related registers of this operation are shown below: INTF (0x11): Interrupt flag
Bit 7 Bit 6 Bit 5 Bit 4 PWM0IF Bit 3 EINT1F Bit 2 EINT0F Bit 1 TCCOF Bit 0 FRCOF
DT0L (0x21): Duty of PWM0 low byte
Bit 7 DT07 Bit 6 DT06 Bit 5 DT05 Bit 4 DT04 Bit 3 DT03 Bit 2 DT02 Bit 1 DT01 Bit 0 DT00
DT0H (0x22): Duty of PWM0 high byte
Bit 7 DT0F Bit 6 DT0E Bit 5 DT0D Bit 4 DT0C Bit 3 DT0B Bit 2 DT0A Bit 1 DT09 Bit 0 DT08
DL0L (0x25): Duty latch of PWM0 low byte
Bit 7 DL07 Bit 6 DL06 Bit 5 DL05 Bit 4 DL04 Bit 3 DL03 Bit 2 DL02 Bit 1 DL01 Bit 0 DL00
DL0H (0x26): Duty latch of PWM0 high byte
Bit 7 DL0F Bit 6 DL0E Bit 5 DL0D Bit 4 DL0C Bit 3 DL0B Bit 2 DL0A Bit 1 DL09 Bit 0 DL08
The PWM duty cycle is defined by writing to the DTX register, and is latched from DTX to DLX while TMRX is cleared. When DLX is equal to TMRX, the PWMX pin is cleared. DTX can be loaded at any time. However, it cannot be latched into DLX until the current value of DLX is equal to TMRX. The following formula describes how to calculate the PWM duty cycle: Duty Cycle = (DTX+1) * (2/Fosc) PRD0L (0x23): Period of PWM0 low byte
Bit 7 PRD07 Bit 6 PRD06 Bit 5 PRD05 Bit 4 PRD04 Bit 3 PRD03 Bit 2 PRD02 Bit 1 PRD01 Bit 0 PRD00
PRD0H (0x24): Period of PWM0 high byte
Bit 7 PRD0F Bit 6 PRD0E Bit 5 PRD0D Bit 4 PRD0C Bit 3 PRD0B Bit 2 PRD0A Bit 1 PRD09 Bit 0 PRD08
The PWM period is defined by writing to PRDX. When TMRX is equal to PRDX, the following events occur on the next increment cycle: TMRX is cleared The PWMX pin is set to 1.
84 * Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
EM77930
USB+BB Controller
The PWMX duty cycle is latched from DTPS to DUTY.
NOTE The PWMX will not be set if the duty cycle is 0.
The PWMXIF pin is set to 1. The following formula describes how to calculate the PWM period: PERIOD = (PRD +2) * (2/Fosc) The PWM function must be disabled before a new period is executed. In other words, bit PWMXE has to be reset in advance, if the contents of PRDX are reloaded. PRIE (0x80): Peripherals enable control
Bit 7 Bit 6 USBE Bit 5 BBE Bit 4 Bit 3 Bit 2 PWM0E Bit 1 TCCE Bit 0 FRCE
INTE (0x81): Interrupt enable control
Bit 7 GIE Bit 6 Bit 5 Bit 4 PWM0IE Bit 3 EINT1E Bit 2 EINT0E Bit 1 TCCOE Bit 0 FRCOE
PWMCR (0x98): PWM control
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 S_PWM0 Bit 1 Bit 0 -
10.3 PWM Programming Procedures/Steps
(1) Load PRDX with the PWMX period. (2) Load DTX with the PWMX Duty Cycle. (3) Enable interrupt function by setting PWMXIE in the INTE register, if required. (4) Set the PWM pin as output by setting PWMCR.S_PWMX. (5) Enable the PWM function by setting the PWMXE bit in the PRIE register. (6) Write the desired new duty to DTX before TMRX is equal to PRDX, then this new DTX will be latched into DLX if various duty cycle is required for next the PWMX operation. (7) Clear the PWMXE bit and write the desired new period to PRDX, then enable it again if various periods are required for the next PWMX operation. (8) Clear the PWMXIF before the next operation if interrupt PWMXIE is employed.
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
* 85
EM77930
USB+BB Controller
11 Interrupts
11.1 Introduction
The EM77930 has 17 interrupt sources. By priority, these interrupts are classified into three levels, namely; peripherals, baseband, and USB, and described as following: The interrupt status registers record the interrupt requests in the corresponding control bits in the interrupt control registers. The global interrupt (GIE) is enabled by the ENI instruction and is disabled by the DISI instruction. The interrupt flag bit must be cleared by instructions before leaving the interrupt service routine to avoid recursive interrupts. The flags in the Interrupt Status Register are set regardless of the status of their corresponding mask bits or the execution of DISI. Note that the logic AND of an interrupt flag and its corresponding interrupt control bit is 1 which makes the program counter point to the right interrupt vector. Refer to Fig. 11. The RETI instruction ends the interrupt routine and enables the global interrupt (the execution of ENI). Before the interrupt subroutine is executed, the contents of ACC, SR, RAMBS0 and ROMPS will be saved by the hardware. After the interrupt service routine is finished, ACC, SR, RAMBS0 and ROMPS will be pushed back. In the EM77930, individual interrupt sources have their own interrupt vectors, depicted in the following table:
No Mnemonic Mask 1 2 KWUAE KWUBE EINT0E EINT1E Status KWUAIF KWUBIF EINT0F EINT1F FRCOF TCCOF PWM0IF CSDF TX_AEF RX_AFF TX_EMPTYF RX_OFF LINK_DIS 1 1 1 1 1 2 2 2 2 2 2 0x10 Key Wake Up 0x18 External Interrupt 0x20 FRC Overflow 0x28 TCC Overflow 0x40 0x48 0x50 0x58 PWM period complete Carrier sense interrupt TX FIFO almost empty RX FIFO almost full Priority Vector Function Mask Status
Register Bit Register Bit 0x82 0x83 0x81 0x81 0x81 0x81 0x99 0x99 0x99 0x99 0x99 0x99 3~0 All 2 3 0 1 4 7 6 5 4 3 2 0x12 013 0x11 0x11 0x11 0x11 0x30 0x30 0x30 0x30 0x30 0x30 3~0 All 2 3 0 1 4 7 6 5 4 3 2
3 FRCOE 4 TCCOE 5 PWM0IE 6 CSDE 7 TX_AEE 8 RX_AFE 9 TX_EMPTY 10 RX_OFE 11 LINK_DIS
0x60 TX FIFO empty 0x68 RX FIFO overflow 0x70 LINK_DIS interrupt
86 *
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
EM77930
USB+BB Controller
No
Mnemonic Mask Status
Priority Vector 2 2 3 3 3 3 3 3 3 0x88
Function
Mask
Status
Register Bit Register Bit 0x78 Lock out interrupt 0x80 Lock in interrupt EP0 USB RX Event EP0 USB TX Event EP0 USB IN Token Event EP1 Interrupt 0x90 EP2 Interrupt EP3 Interrupt USB Bus Reset Event Detect USB Bus Suspend Event Detect 0x98 USB Bus Resume Event Detect Function Remote Wake-Up Interrupt 0XA8 Start Of Frame Interrupt 0x99 0x99 0x1D2 0x1D2 0x1D2 0x1D2 0x1D2 0x1D2 0x1D4 1 0 0 1 2 3 4 5 0 0x30 0x30 0x1D1 0x1D1 0x1D1 0x1D1 0x1D1 0x1D1 0x1D3 1 0 0 1 2 3 4 5 0
12 LOCK_OUTE LOCK_OUTF 13 LOCK_INE 14 INT0RXE 14 INT0TXE 14 INT0INE 15 INT1E 15 INT2E 15 INT3E 16 RSTINTE LOCK_INF INT0RXF INT0TXF INT0INF INT1F INT2F INT3F RSTINTF
16 IDLEINTE
IDLEINTF
3
0x1D4
1
0x1D3
1
16 RUEINTE
RUEINTF
3
0x1D4
2
0x1D3
2
16 FRWPINTE FRWPINTF
3
0x1D4
3
0x1D3
3
17 SOFINTE
SOFINTF
3
0x1E8
6
0x1E7
6
The interrupt priority is another useful feature provided by this IC. The latest interrupt, which has the highest priority than the others, will override and hold the currently executed interrupt until the interrupt is finished. Otherwise, the latest interrupt will be in queue right after all its peers.
Global INT Enable Function INT Enable Function INT Flag
Fig. 11 Block Diagram of Interrupts
Function INT Condition Occured
Function INT Vector Address
Function Enable
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
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USB+BB Controller
12 Circuitry of Input and Output Pins
12.1 Introduction
The EM77930 has five parallel ports, namely: Port A, Port B, Port C, Port D and Port F which only two least significant bits are available. That is, there are 30 available I/O pins. A control bit defines the configuration of its corresponding pin. Refer to Fig. 3-1 for the Pin Assignment. The I/O registers, from Port A to Port F, are bidirectional tri-state I/O ports. The I/O ports can be defined as "input" or "output" pins by the I/O control registers (IOCA, IOCB, IOCC, IOCD and IOCF) under program control. The I/O registers and I/O control registers are both readable and writable. Note that the source is different between the reading path of input and output pin while reading the I/O port.
13 Timer/Counter System
13.1 Introduction
The EM77930 provides two timer modules: 8-bit TCC (Timer Clock/Counter), and 16-bit FRC (Free Run Counter). The TCC clock source comes from one of the instruction cycle and low frequency oscillator (IRC). The FRC clock source is from either instruction cycle or low frequency oscillator (IRC).
13.2 Time Clock Counter (TCC)
An 8-bit counter is available as prescaler for the TCC. The prescaler ratio is determined by the PS0~PS2 bits. When in TCC mode, the prescaler is cleared each time an instruction writes to the TCC. TCC is an 8-bit timer/counter. If the TCC signal source is from the system clock, TCC will be incremented by 1 in every instruction cycle (without prescaler). If the TCC signal source is from the IRC clock input, the TCC will be incremented by 1 on every falling edge or rising edge of the TCC pin. The prescaler counter (PRC) can be read from Address 0x0F. In other words, the combination of TCC and PRC can be used as a 16-bit counter without prescaler.
88 *
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
EM77930
USB+BB Controller
13.2.1 Block Diagram of TCC
TCCS0 TCCE Data Bus
Fosc
0 M U X PRC (8- bit Counter) Sync with Internal Clock 2 clocks delay TCCOF TCC
ERC
1
PS0
PS1
PS2
8-1 MUX
Fig. 13-1 Function Block Diagram of TCC
13.2.2 TCC Control Registers
As the TCC mode is defined, the related registers involved in this operation are shown below: PRC (0x0F): Prescaler counter TCC (0x10): Timer clock/counter INTF (0x11): Interrupt flag
Bit 7 Bit 76 Bit 75 Bit 74 PWM0IF Bit 73 EINT1F Bit 72 EINT0F Bit 71 TCCOF Bit 70 FRCOF
PRIE (0x80): Peripherals enable control
Bit 7 Bit 76 USBE Bit 75 BBE Bit 74 Bit 73 Bit 72 PWM0E Bit 71 TCCE Bit 70 FRCE
INTE (0x81): Interrupt enable control
Bit 7 GIE Bit 76 Bit 75 Bit 74 PWM0IE Bit 73 EINT1E Bit 72 EINT0E Bit 71 TCCOE Bit 70 FRCOE
TCCC (0x93): Timer clock/counter control
Bit 7 Bit 76 Bit 75 Bit 74 Bit 73 TCCS0 Bit 72 PS2 Bit 71 PS1 Bit 70 PS0
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
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USB+BB Controller
13.2.3 TCC Programming Procedures/Steps
(1) Load TCCC with the prescaler and TCC clock source. (2) Load the TCC with the TCC overflow period. (3) Enable the interrupt function by setting TCCOE in the INTE register, if required. (4) Enable the TCC function by setting the TCCE bit in the PRIE register. (5) Wait for either the interrupt flag to be set (TCCOF) or the TCC interrupt to occur. (6) The following formula describes how to calculate the TCC overflow period:
1 TCC Timer = (0 x 100 - TCC ) x Pr escaler ClockSource
where Clock Source = Fosc or IRC
13.3 Free Run Counter
Dual 8-bit counters, high byte register and low byte register, make up the 16-bit software programmable counter. The driving clock source is either the system clock divided by 2 or the low frequency oscillator. A read of the low byte register allows full control of the corresponding timer function. On the contrary, accessing a high byte register will inhibit the specific timer function until the corresponding low byte is read as well.
13.3.1 Block Diagram of FRC
FRCE FRCCS
Fosc
0 M U X Sync with Internal Clock
LFRF
HFRC
FRCOF
ERC
1 LFRFB Data Bus
Fig. 13-2 Timer 1 Function Block Diagram
90 *
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
EM77930
USB+BB Controller
13.3.2 FRC Control Registers
As the FRC mode is defined, the related registers involved in this operation are shown below: INTF (0x11): Interrupt flag.
Bit 7 Bit 76 Bit 75 Bit 74 PWM0IF Bit 73 EINT1F Bit 72 EINT0F Bit 71 TCCOF Bit 70 FRCOF
LFRC (0x1A): Least significant byte of 16-bit free run counter. HFRC (0x1B): Most significant byte of 16-bit free run counter. LFRCB (0x1C): Least significant byte buffer of 16-bit free run counter. PRIE (0x80): Peripherals enable control
Bit 7 Bit 76 USBE Bit 75 BBE Bit 74 Bit 73 Bit 72 PWM0E Bit 71 TCCE Bit 70 FRCE
INTE (0x81): Interrupt enable control
Bit 7 GIE Bit 76 Bit 75 Bit 74 PWM0IE Bit 73 EINT1E Bit 72 EINT0E Bit 71 TCCOE Bit 70 FRCOE
FRCC (0x94): Free run counter control.
Bit 7 Bit 76 Bit 75 Bit 74 Bit 73 Bit 72 PPSCL1 Bit 71 PPSCL0 Bit 70 FRCCS
OCSO2E OSCO2SL1 OSCO2SL0 PPSCL2
13.3.3 FRC Programming Procedures/Steps
(1) Load the LFRCB with the FRC overflow period low byte. (2) Load the HFRC with the TCC overflow period high byte. Then the LFRC will automatically load with the LFRCB. (3) Enable the interrupt function by setting FRCOE in the INTE register, if required. (4) Enable FRC function by setting the FRCE bit in the PRIE register. (5) Wait for either the interrupt flag to be set (FRCOF) or the FRC interrupt to occur. (6) A low byte access on the 16-bit counter receives the count value at the instance of reading. However, the low byte contents will be transferred to the buffer, the LFRCB register, if a high byte is read first. The value in the LFRCB register remains unchanged until the corresponding low byte is read. (7) The following formula describes how to calculate the FRC overflow period:
1 FRC Timer = (0 x100 - HFRC : LFRC )x ClockSource
where Clock Source = Fosc or IRC
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
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USB+BB Controller
14 Reset and Wake Up
14.1 Reset
The reset can be caused by one of the following: (1) Power-on reset (2) /RESET pin input "low", or (3) Watchdog timer time-out (if enabled) The device will remain in a reset condition for a period of 8-bit internal RC ripple counter (one oscillator start-up timer period) after the reset is detected. The initial Address is 000h.
14.2 The Status of RST, T, and P of STATUS Register
A reset condition can be caused by the following events: (1) A power-on condition (external); (2) A high-low-high pulse on the /RESET pin (external); and (3) Watchdog timer time-out (internal). The values of bits RST, T and P, listed in Table 14.1 can be used to check how the processor wakes up. Table 14.1 Values of RST, T and P after a reset
Condition Power on WDTC instruction WDT timeout SLEP instruction Wake-Up on pin change during Sleep mode RST 0 *P *P *P 1 T 1 1 0 *P 1 P 1 *P *P 0 0
*P: Previous status before reset
14.3 System Set-up (SSU) Time
In order to have a successful start up, System Set-up Time (SSU) is employed to guarantee a stable clock for IC operation. It is made up of two delay sources: (1) Internal RC Oscillation Set-up Delay (IRCOSUD): Internal RC oscillation shared with a watchdog timer divided by a 6-bit ripple counter. The RC delay controlled by bit IRCDE in the Code Option is optional. (2) Main Oscillation Set-up Delay (MOSUD): A 10-bit ripple counter is used to filter unstable main clocks at the beginning of power-on before the chip starts to run. This delay is performed right after IRCOSUD, if enabled.
92 *
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
EM77930
USB+BB Controller
OSC1
10-bit Ripple Counter
SSU
6-bit Ripple Counter
Internal RC Osc .
RCSUTE
Fig. 13 System Set-up Time
14.4 Wake-up Procedure on Power-on Reset
Power-on Voltage Detector (POVD) will allow the VDD whose value is over the default threshold voltage (2.0 V for the EM77930) enter the IC, and the SSU delay starts. The following three cases may be taken into consideration: (1) /RESET pin goes high with VDD at the same time. In hardware, this pin and VDD are tied together. The internal reset will remain low until the SSU delay is over. (2) /RESET pin goes high during the SSU delay. It is similar to Case 1. The IC will start to operate as the SSU delay is over. /RESET pin goes high after the SSU delay. The EM77930 will start program execution immediately.
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
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USB+BB Controller
15 Oscillators
15.1 Introduction
The EM77930 provides three main oscillators: One high frequency crystal oscillator (connected to OSCI), internal RC, and four PLL (Phase Lock Loop) Outputs. Versatile combinations of oscillation are provided for wild applications. On-chip clock sources can be either dual clocks or single clock.
15.2 Clock Signal Distribution
USB
BYP
RF-BB
16 bit PWM
SYS_CLK 0/1=0 & RF_CLK 0/1=0 & USB_CLK=0 BYP 6 MHz PLL PD (Power Down) 6 12 24 48
RF_CLK 0/1 SR.GREEN SYS_NCLK
MCU Kernel
SYS_CLK 0/1 SYS_ICLK
IRC CLK
TCCC.TCCS0
FRCC.FRCCS
WDT
8 bit TCC
16 bit FRC
Fig. 14 Clock Tours
15.3 PLL Oscillator
The Phase-locked loop (PLL) technology is employed to produce four different frequencies: 6 MHz, 12MHz, 24MHz and 48 MHz (external 6MHz crystal). 6 MHz is the system clock source and 48 MHz is USB device and Hub clock source only. PLL is enabled except when entering Green and Sleep mode.
94 *
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
EM77930
USB+BB Controller
16 Low-Power Mode
16.1 Introduction
The EM77930 has two power-saving modes, green mode and sleep mode. Figure 16 shows the mode change diagram.
Power On
Normal
1. Key Wake-up 2. WDT Time out 3. /Reset
WDTC[7].Green=0 SLEP INST. Key Wake up 1. WDTC[7].Green=1 2. WDT Time out 3. /Reset
Green
SLEP INST.
Sleep
Fig. 16 Three Mode State
16.2 Green Mode
The "GREEN" bit of WDTC [7] register is the only control bit used for mode switching, between normal mode and green mode. Its initial value is "0", normal mode. When "GREEN" bit is written with a 1, the MCU will switch to green mode from normal mode. In contrast, the MCU will go back to normal mode when the "GREEN" bit is written from 1 to 0. During green mode, the main oscillator will be turned off. The MCU and all the peripherals are driven by the external RC oscillator - IRC. Once RF peripheral is functional and then switched into green mode, the clock source for all the other peripherals, except PLL, will be provided by IRC. PLL will keep running as RF circuit's clock source.
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
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USB+BB Controller
16.3 Sleep Mode
The execution of "SLEP" instruction will turn the whole chip into Sleep mode. The main clock will be shut down. The IRC oscillator is halted also if the watchdog function is disabled. All registers, memory and I/O port remain in their previous states during sleep mode. The overflow of the watchdog timer driven by IRC will generate a reset to resume normal operation. Key Wake up (KWU) interrupt and /RESET pin are other methods to exit sleep mode. It is essential to wait for stable Oscillation start up time before normal operation. The stabilizing time is SST.
17 Instruction Description
17.1 Instruction Set Summary
Type Instruction Binary 0000 0000 0000 0000 System Control 0000 0000 0000 0000 1010 1010 1010 0000 0000 0000 0011 1010 0000 0000 0000 0000 0000 0001 0010 0000 0000 0000 1101 1011 0000 0000 0000 0000 rrrr rrrr rrrr 0000 0000 0000 0000 kkkk 0100 0101 0110 0111 rrrr rrrr rrrr 1010 1011 1100 0010 kkkk SLEP ENI DISI DAA TBRDP r TBRD r TBRDM r TBRDP A TBRD A TBRDM A TBL RETL #k 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 0010 0011 Mnemonic NOP WDTC RET RETI Operation No operation WDT 0 PC (Top of Stack) PC (Top of Stack); Enable Interrupt WDT 0 Stop oscillator Enable Interrupt Disable Interrupt Decimal Adjust A r ROM[(TABPT[15:1])] TABPT TABPT+1 r ROM[(TABPT[15:1])] r ROM[(TABPT[15:1])] TABPT TABPT-1 A ROM[(TABPT[15:1])] TABPT TABPT+1 A ROM[(TABPT[15:1])] A ROM[(TABPT[15:1])] TABPT TABPT-1 R2 R2+A Ak PC [Top of Stack] Status Affected None None None None None None None C None None None None None None C, DC, Z None Cycles 1 1 1 1 1 1 1 1 2 2 2 2 2 2 1 1
Table Look up
96 *
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
EM77930
USB+BB Controller
Type
Instruction Binary 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 00kk 01kk 10kk 11kk 10kk 11kk 0bbb aaaa 1bbb aaaa 0010 aaaa 0011 aaaa 0100 aaaa 0101 aaaa rrrr rrrr Rrrr Rrrr Rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr
Mnemonic rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr OR A, r OR r, A AND A, r AND r, A XOR A, r XOR r, A COMA r COM r RRCA r, #k RRC r, #k RLCA r, #k RLC r, #k SHRA r, #k SHLA r, #k
Operation A A .or. r r r .or. A A A .or. k A A .and. r r r .and. A A A .and. k A A .xor. r r r .xor. A A A .xor. k A /r r /r [C,r] rotate right k bits to [C,A] [C,r] rotate right k bits to [C,r] [C,r] rotate left k bits to [C,A] [C,r] rotate left k bits to [C,r] [C,r] shift right k bits to A Insert C into high order bits [C,r] shift left k bits to A Insert C into low order bits If r(b)=0, jump to addr If r(b)=1, jump to addr A r-1, jump to addr if zero r r-1, jump to addr if zero Ar+1, jump to addr if zero r r+1, jump to addr if zero
Status Affected Z Z Z Z Z Z Z Z Z Z Z C C C C None None None None None None None None
Cycles 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2/3* 2/3* 2/3* 2/3* 2/3* 2/3*
kkkk kkkk OR A, #k
kkkk kkkk AND A, #k
kkkk kkkk XOR A, #k
Logic
0000 1011 1011 1011 1011 0101 0101 0001 xxaa 0001 xxaa 0101
JBC aaaa aaaa r,b,addr JBS aaaa aaaa r,b,addr rrrr rrrr DJZA aaaa aaaa r,addr rrrr rrrr rrrr rrrr rrrr rrrr aaaa aaaa aaaa aaaa aaaa aaaa DJZ r,addr JZA r,addr JZ r,addr
Compare Branch
xxaa 0101 xxaa 0101 xxaa 0101 xxaa
Note: *Condition for successful instruction execution needs 2/3 cycles (jump to address).
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
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USB+BB Controller
Type
Instruction Binary 0010 0010 0011 0011 0bbb 1bbb 0bbb 1000 1001 1100 0000 1111 1100 1101 1110 0010 0011 0100 1110 1111 0000 0001 1000 1001 rrrr rrrr rrrr rrrr rrrr rrrr 0000 rrrr rrrr rrrr kkkk rrrr rrrr kkkk rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr
Mnemonic BC r,b BS r,b BTG r,b SWAP r SWAPA r ZCHK r RPT CLR r ADD A,r ADD r,A ADD A,#k SUB A,r SUB r,A SUB A,#k INCA r INC r DECA r DEC r MOV A,r MOV r,A
Operation r(b) 0 r(b) 1 r(b) /r(b) r(0:3) r(4:7) A(4:7) r(0:3) A(0:3) r(4:7) Z 0 if r < > 0 Single repeat CS times on next TBRD instruction r0 A A+r r r+A A A+k A r-A f r-A A k-A A r+1 r r+1 A r-1 r r-1 Ar r A
Status Affected None None None None None Z None Z C, DC, Z C, DC, Z C, DC, Z C, DC, Z C, DC, Z C, DC, Z C, DC, Z C, DC, Z C, DC, Z C, DC, Z Z None None None None
Cycles 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Process
0011 1010 0000 1010 0011 0011 0011 0100 0100 0100 0100 0100 0101 0101 1010 1010
1101 rrrr rrrr rrrr kkkk rrrr rrrr kkkk rrrr rrrr rrrr rrrr rrrr rrrr
Arithmetic
Move
0110 1010 110a
r2 r2 r2 r2 r2 r2 r1 r1 r1 r1 r1 r1 MOVRR r1, r2 Register r1 Register r2 0111 aaaa kkkk aaaa kkkk aaaa MOV A,#k JMP addr Ak PC addr PC[13..16] unchange [Top of Stack] PC + 1 PC addr PC [13..16] unchange
Branch 111a aaaa aaaa aaaa CALL addr
None
1
Bank Page
1010 1010
1110 1101
0000 0000
0kkk 000k
BANK #k PAGE #k
R4(RAMBS0) k (0~6) R5(PAGES) k (0~1)
None None
1 1
98 *
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
EM77930
USB+BB Controller
18 Electrical Specification
18.1 Absolute Maximum Ratings
Temperature Under Bias Storage temperature Input voltage Output voltage 0C -65C -0.3V -0.3V to to to to 70C 150C +3.6V +3.6V
18.2 DC Electrical Characteristic
Ta=0C ~ 70 C, VDD=3.3V5%, VSS=0V
Symbol Fxt IIL VIH VIL VIHT VILT VIHX VILX Parameter Condition Min DC -
0.8xVDD
Typ - - - - - - - - -
Max 48.0 2 -
0.2xVSS
Unit MHz A V V V V V V V
Crystal: VDD ~ 2.75V One cycle with one clock Input Leakage VIN = VDD, VSS Current for input pins Input High Voltage Input Low Voltage Port A ~ Port F Port A ~ Port F
VSS 2.0 - 2.5 - 2.4
Input High Threshold /RST Voltage Input Low Threshold /RST Voltage Clock Input High Voltage Clock Input Low Voltage OSCI, OSCO OSCI, OSCO
- 0.8 - 1.0 -
Output High Voltage: VOH1 PTA, PTC, PTD, IOH = -8.0 mA PTE, PTF Output High Voltage: VOH2 PTB; IOH = -8.0 mA RFIO VOL1 VOL2 IPH ISB Output Low Voltage: IOL = 8.0 mA PTA, PTC, PTD, PTE, PTF Output Low Voltage: IOL = 8.0 mA (1) PTB; RFIO Pull-high current Pull-high active, input pin at VSS
2.4
-
-
V
- - - -
- - -6.5 -
0.4 0.4 - -
V V A A
All input and I/O pins at VDD, Power down current Output pin floating, WDT and all peripherals disabled. Operating supply current (VDD = 3.3V) Operating supply current (VDD = 3.3V) /RESET = 'High', Fosc = 32kHz (RC type), Output pin floating, WDT and all peripherals disabled. /RESET= 'High', Fosc = 6MHz (Crystal type), Output pin floating, and all peripherals disabled.
ICC1
-
10
-
A
ICC3
-
6
-
mA
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
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USB+BB Controller
18.3 Voltage Detector Electrical Characteristic
Ta=25C
Symbol Vdet Vrel Iss Vop Vdet/Ta Parameter Detect voltage Release voltage Current consumption Operating voltage Vdet Temperature characteristic Condition - - VDD = 3V - 0C Ta 70C Min 1.8 - - 0.7* - Typ 2.0
Vdet x 1.05
Max 2.2 - 0.8 3.5 -2
Unit V V A V
MV/C
- - -
* When the voltage of VDD rises between Vop=0.7V and Vdet, the voltage detector output
must be "Low".
18.4 AC Electrical Characteristic
18.4.1 MCU
Ta=0C ~ 70 C, VDD=3.3 V5%, VSS=0V)
Symbol Dclk Tins Ttcc Tdrh Trst Twdt Tset Thold Tdelay Parameter Input CLK duty cycle Instruction cycle time (CLKS="0") TCC input period Device reset hold time /RESET pulse width Watchdog timer period Input pin setup time Input pin hold time Output pin delay time Conditions - Crystal type RC type - Ta = 25C Ta = 25C Ta = 25C - - Cload=20pF Min 45 125 500
(Tins+20)/N*
Typ 50 - - 18 - 18 0 20 50
Max 55 DC DC - 30 - 30 - - -
Unit % ns ns ns ms ns ms ms ms ms
9 2000 9 - - -
* N= selected prescaler ratio.
100 *
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
EM77930
USB+BB Controller
18.4.2 BB
Ta=0C ~ 70 C, VDD=3.3 V5%, VSS=0V
Symbol 1/tOSC tRDPW tCSRD tADRD tRDDV tRHDT tDHAR tRHDT tRDAN Parameter Oscillator frequency RD pulse width CS low to RD low Address valid for RD low RD low to Data valid Data float after RD. Data hold after RD Time between consecutive RD pulses Address valid after RD low Min 0.1 3*tOSC+ tOSC 0 - - 0 2*tOSC 3*tOSC+ Max 24 - - - 3*tOSC+ tOSC - - - Unit MHz ns ns ns ns ns ns ns ns
>0 will be determined according to cell library simulation. The values above were determined according to behavioral simulations. They take into account only the BB digital state-machine. Thus, such values are for reference only.
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
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USB+BB Controller
19 Application Circuit
EM77930
Fig. 18 USB Keyboard Circuit
Keyboard Setting: Port A, Port C, Port D: Key Scan Column Port B: Key Scan Row Port F.1: Scroll Lock LED Port F.2: Caps Lock LED Port F.3: Num Lock LED
102 *
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
EM77930
USB+BB Controller
20 Pad Description
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
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USB+BB Controller
Pad Name & Pad Coordinates Table Structure Name: EM77930 Chip Size3114 X 3116 Pin No. 1 2 3 4 5 6 7 8 9 9 10 11 12 13 13 13 14 15 16 17 18 19 20 21 22 Pad Name PA1 PA2 PA3 RST PA4 PA5 PA6 PA7 GND: GND: UPRT_DP UPRT_DM VDD_5V VUSB_33V VDD: VDD: PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 RF_ACT X 97.1 97.1 97.1 97.1 97.1 97.1 97.1 97.1 97.1 97.1 100.508 100.508 433.316 757.53 961.252 1149.099 1348.453 1532.693 1719.98 1907.234 2094.063 2282.768 2466.56 2656.054 2844.284 Y 2844.874 2632.001 2421.65 2207.793 1996.14 1783.585 1574.051 1359.377 1147.191 915.239 637.237 442.737 97.1 97.1 97.1 97.1 97.1 97.1 97.1 97.1 97.1 97.1 97.1 97.1 97.1 Pin no. 23 24 25 26 27 28 28 29 30 31 32 33 34 35 36 37 38 39 39 40 41 42 43 44 Pad Name TX_RX RFIO PC3 PC4 PLLC GND: GND: OSCI OSCO2 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 VDD: VDD: PF0 PF1 PF2 PF3 PA0 X 3016.428 3016.428 3016.428 3016.428 3016.428 3016.428 3016.428 3016.428 3016.428 3016.428 3016.428 2804.123 2613.123 2424.929 2243.899 2072.155 1913.055 1709.377 1197.71 1007.255 834.279 667.244 479.878 279.011 Y 283.77 473.951 659.981 834.832 1008.099 1677.167 1849.461 2062.597 2543.513 2714.764 2891.764 3017.411 3017.411 3017.411 3017.411 3017.411 3017.411 3017.411 3017.411 3017.411 3017.411 3017.411 3017.411 3017.411 Structure Name:
104 *
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
EM77930
USB+BB Controller
APPENDIX A Package Type
ET NO EM77930 Package Type LQFP48 Pin Count 48 Package Size 7X7MM
B Package Information
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)
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USB+BB Controller
106 *
Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)

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